18493993. Shared Control Bus for Graphics Processors simplified abstract (Apple Inc.)
Contents
Organization Name
Inventor(s)
Jonathan M. Redshaw of St. Albans (GB)
Ali Rabbani Rankouhi of Bushey (GB)
This abstract first appeared for US patent application 18493993 titled 'Shared Control Bus for Graphics Processors
Simplified Explanation
- Techniques for a shared control bus for communicating between primary control circuitry and multiple distributed graphics processor units. - Set of multiple graphics processor units including at least first and second graphics processors on different semiconductor substrates packaged in a multi-chip module. - Graphics processors are coupled to access graphics data via respective memory interfaces. - Shared workload distribution bus includes interfaces between graphics processors on the same substrate and cross-substrate interfaces between different substrates. - Workload distribution circuitry transmits control data specifying graphics work distribution to the multiple graphics processor units. - Packet control circuitry modifies packets from interfaces for transmission via the cross-substrate interface.
Potential Applications
- High-performance computing - Graphics processing units (GPUs) - Data centers - Virtual reality systems
Problems Solved
- Efficient communication between primary control circuitry and multiple graphics processor units - Optimal workload distribution among graphics processors - Enhanced performance and scalability in multi-chip module configurations
Benefits
- Improved graphics processing capabilities - Enhanced system performance and efficiency - Scalability for handling complex workloads - Reduced latency in data communication between processors
Original Abstract Submitted
Techniques are disclosed relating to a shared control bus for communicating between primary control circuitry and multiple distributed graphics processor units. In some embodiments, a set of multiple graphics processor units including at least first and second graphics processors on different semiconductor substrates that are packaged in a multi-chip module, where the first and second graphics processors are coupled to access graphics data via respective memory interfaces. The shared workload distribution bus may include: one or more interfaces between respective graphics processors on the same semiconductor substrate and at least one cross-substrate interface between the different semiconductor substrates. Workload distribution circuitry may transmit, via the shared workload distribution bus, control data that specifies graphics work distribution to the multiple graphics processor units. Packet control circuitry may modify packets from at least one of the one or more interfaces for transmission via the cross-substrate interface.
