18493692. Main Wordline Decoding Circuitry simplified abstract (Micron Technology, Inc.)
Contents
Main Wordline Decoding Circuitry
Organization Name
Inventor(s)
Kevin John Platt of McKinney TX (US)
Mark W. Keefer of Allen TX (US)
Main Wordline Decoding Circuitry - A simplified explanation of the abstract
This abstract first appeared for US patent application 18493692 titled 'Main Wordline Decoding Circuitry
The memory device described in the patent application includes multiple decoding unit circuitries that decode a first set of addressing bits to multiple wordline arming bits, each arming a corresponding wordline. Each decoding unit circuitry consists of multiple sub-units that decode a second set of addressing bits to a subset of the wordline arming bits.
- Each decoding unit circuitry includes multiple sub-units that decode a second set of addressing bits to a subset of wordline arming bits.
- The sub-units contain inverters that invert the addressing bits to output a wordline arming signal.
- A common node is coupled to the inverters and can be decoupled from a common return by transistors.
- Bleed transistors are included in each sub-unit to bleed charge onto the wordline arming signal to prevent a floating condition of the common node.
Potential Applications: - Memory devices - Semiconductor industry - Integrated circuits
Problems Solved: - Efficient decoding of addressing bits - Mitigation of floating conditions in common nodes
Benefits: - Improved memory device performance - Enhanced reliability - Cost-effective solution
Commercial Applications: Title: Advanced Memory Device Decoding Technology This technology can be utilized in various memory devices, leading to faster and more reliable data storage solutions. The semiconductor industry can benefit from the enhanced performance and efficiency offered by this innovation, potentially leading to new market opportunities.
Questions about Memory Device Decoding Technology: 1. How does the use of multiple decoding unit circuitries improve memory device performance?
- The use of multiple decoding unit circuitries allows for efficient decoding of addressing bits, leading to faster and more reliable data retrieval.
2. What role do inverters and bleed transistors play in mitigating floating conditions in common nodes?
- Inverters invert addressing bits to generate wordline arming signals, while bleed transistors help prevent floating conditions by bleeding charge onto the signals.
Original Abstract Submitted
A memory device includes multiple decoding unit circuitries configured to decode a first set of addressing bits to multiple wordline arming bits each configured to arm a corresponding wordline. Each decoding unit circuitry includes multiple sub-units each configured to decode a second set of addressing bits to a respective subset of the multiple wordline arming bits. The multiple sub-units each include an inverter configured to invert the second set of addressing bits and to output a wordline arming signal. The inverter is coupled between a supply voltage and a common node that is configured to be coupled to and decoupled from a common return by one or more transistors of the wordline decoding circuitry. The multiple-sub-units and each include a bleed transistor that is configured bleed charge onto the wordline arming signal to mitigate for a potential floating condition of the common node.
