18490063. CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
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CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME
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CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18490063 titled 'CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME
The chip on film package described in the patent application includes a film substrate with an upper layer extending in opposite directions and a lower layer with a cutting line.
- Two semiconductor chips are placed on the upper layer within the cutting line area.
- Connection wirings are connected to the chips and extend in opposite directions.
- A test pad is connected to the connection wirings and located on the lower layer within the cutting line area.
Potential Applications: - Semiconductor packaging industry - Electronics manufacturing
Problems Solved: - Efficient chip packaging - Improved testing processes
Benefits: - Enhanced chip connectivity - Simplified testing procedures
Commercial Applications: - Semiconductor chip manufacturing companies - Electronics assembly businesses
Questions about the Technology: 1. How does the placement of the semiconductor chips on the film substrate improve the packaging process? 2. What advantages does the test pad location on the lower layer offer in terms of testing efficiency?
Frequently Updated Research: - Stay updated on advancements in semiconductor packaging technologies for potential improvements in chip on film packages.
Original Abstract Submitted
There is provided a chip on film package. The chip on film package includes a film substrate including an upper layer extending in first and second directions opposite to each other and a lower layer facing the upper layer, and having a cutting line formed thereon, first and second semiconductor chips disposed on the upper layer within an area of the cutting line, first and second connection wirings connected to the first and second semiconductor chips and extending toward the first and second directions, respectively, and a test pad connected to at least one of the first and second connection wirings and disposed on the lower layer, within the area of the cutting line.
