18489640. Floating-point Division Circuitry with Subnormal Support simplified abstract (Apple Inc.)
Floating-point Division Circuitry with Subnormal Support
Organization Name
Inventor(s)
Liang-Kai Wang of Austin TX (US)
Ian R. Ollmann of Los Gatos CA (US)
Anthony Y. Tai of San Jose CA (US)
Floating-point Division Circuitry with Subnormal Support - A simplified explanation of the abstract
This abstract first appeared for US patent application 18489640 titled 'Floating-point Division Circuitry with Subnormal Support
Simplified Explanation
- Circuitry for floating-point division is disclosed in the patent application. - The circuitry can generate a subnormal result for a division operation. - It includes floating-point circuitry for performing a reciprocal operation to determine a normalized mantissa value for the reciprocal of the denominator. - Fixed-point circuitry is included to multiply the normalized mantissa value by the numerator's mantissa to generate an initial value. - Control circuitry determines error data for the initial value and generates a final subnormal mantissa result for the division operation based on the error data and initial value. - The patent application also discloses embodiments with multiple modes offering different accuracy guarantees.
Potential Applications
- High-performance computing - Scientific research - Financial modeling
Problems Solved
- Efficient floating-point division - Handling subnormal results accurately - Providing multiple accuracy modes for different applications
Benefits
- Improved accuracy in floating-point division - Efficient handling of subnormal results - Flexibility with multiple accuracy modes for different needs
Original Abstract Submitted
Techniques are disclosed relating to circuitry for floating-point division. In some embodiments, the circuitry is configured to generate a subnormal result for a division operation that divides a numerator by a denominator. The circuitry may include floating-point circuitry configured to perform a reciprocal operation to determine a normalized mantissa value for the reciprocal of a floating-point representation of the denominator. The circuitry may further include fixed-point circuitry configured to multiply a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value. Control circuitry may determine error data for the initial value and generate a final subnormal mantissa result for the division operation based on the error data and the initial value. Embodiments with multiple modes with different accuracy guarantees are disclosed.
