18480310. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

SEMICONDUCTOR PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Sang Cheon Park of Hwaseong-si (KR)

Dae-Woo Kim of Suwon-si (KR)

Taehun Kim of Asan-si (KR)

Hyuekjae Lee of Hwaseong-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18480310 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The semiconductor package described in the patent application includes a redistribution substrate, a memory chip, a logic chip, and a molding layer. The memory chip is provided on the redistribution substrate and consists of a base layer, a circuit layer, and a via connecting the circuit layer to the substrate. The logic chip is placed on top of the memory chip, and both are surrounded by a molding layer. The interface between the logic chip and the memory chip includes chip pads made of the same material and forming a single body.

• The patent application describes a semiconductor package with a unique structure that allows for efficient integration of memory and logic chips.
• The memory chip is connected to the redistribution substrate through a via, enabling improved electrical connectivity.
• The molding layer surrounding the memory and logic chips provides protection and stability to the package.
• The coplanar side surfaces of the molding layer and logic chip enhance the overall compactness and aesthetics of the package.

Potential applications of this technology:

• This semiconductor package can be used in various electronic devices, such as smartphones, tablets, and computers, to enhance their memory and logic capabilities.
• It can also be applied in automotive electronics, IoT devices, and other embedded systems that require efficient integration of memory and logic functions.

Problems solved by this technology:

• The semiconductor package addresses the challenge of integrating memory and logic chips in a compact and efficient manner.
• The via connection between the memory chip and redistribution substrate improves electrical performance and signal transmission.
• The coplanar side surfaces of the molding layer and logic chip solve the issue of uneven or protruding surfaces in traditional packaging methods.

Benefits of this technology:

• The semiconductor package allows for increased memory and logic capabilities in electronic devices without significantly increasing their size.
• The improved electrical connectivity and signal transmission enhance the overall performance and reliability of the package.
• The compact and aesthetically pleasing design of the package improves the visual appeal and user experience of electronic devices.

Original Abstract Submitted

A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.