18474111. DIE PAIR DEVICE PARTITIONING simplified abstract (ADVANCED MICRO DEVICES, INC.)
Contents
DIE PAIR DEVICE PARTITIONING
Organization Name
Inventor(s)
Samuel Naffziger of Fort Collins CO (US)
William George En of Santa Clara CA (US)
John Wuu of Fort Collins CO (US)
DIE PAIR DEVICE PARTITIONING - A simplified explanation of the abstract
This abstract first appeared for US patent application 18474111 titled 'DIE PAIR DEVICE PARTITIONING
The abstract describes a method for die pair partitioning in an integrated circuit, involving connecting multiple circuit dies with different functionalities.
- Circuit die with metal stack and logic transistors
- Additional circuit die with metal stacks connected to the first die
- Majority of static random access memory and analog devices on additional dies
- Connection of metal stacks between circuit die and additional dies
Potential Applications: - Semiconductor manufacturing - Integrated circuit design - Electronic device production
Problems Solved: - Efficient partitioning of different functionalities in an integrated circuit - Optimization of die pair connections for improved performance
Benefits: - Enhanced functionality in integrated circuits - Streamlined manufacturing processes - Improved overall performance of electronic devices
Commercial Applications: Title: "Die Pair Partitioning Method for Integrated Circuits" This technology can be utilized in the semiconductor industry for designing and manufacturing complex integrated circuits, leading to improved performance and functionality in electronic devices.
Prior Art: Readers can explore prior research in die partitioning methods in integrated circuits, as well as advancements in semiconductor manufacturing techniques.
Frequently Updated Research: Stay informed about the latest developments in die pair partitioning methods for integrated circuits to ensure optimal performance and efficiency in electronic devices.
Questions about Die Pair Partitioning: 1. How does die pair partitioning contribute to the overall efficiency of integrated circuits? 2. What are the key considerations in connecting multiple circuit dies with different functionalities in an integrated circuit?
Original Abstract Submitted
A method for die pair partitioning can include providing a circuit die that has a metal stack and that includes a majority of logic transistors of an integrated circuit. The method can also include providing one or more additional circuit die that have one or more additional metal stacks of which at least one is connected to the metal stack of the circuit die and a majority of static random access memory and analog devices of the integrated circuit. The method can further include connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die. Various other methods, systems, and computer-readable media are also disclosed.
