18469905. Read Arbiter Circuit with Dual Memory Rank Support simplified abstract (Apple Inc.)
Contents
- 1 Read Arbiter Circuit with Dual Memory Rank Support
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Read Arbiter Circuit with Dual Memory Rank Support - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
Read Arbiter Circuit with Dual Memory Rank Support
Organization Name
Inventor(s)
Shane J. Keil of San Jose CA (US)
Gregory S. Mathews of Saratoga CA (US)
Lakshmi Narasimha Murthy Nukala of Pleasanton CA (US)
Read Arbiter Circuit with Dual Memory Rank Support - A simplified explanation of the abstract
This abstract first appeared for US patent application 18469905 titled 'Read Arbiter Circuit with Dual Memory Rank Support
Simplified Explanation
The memory control circuit described in the patent application is designed to efficiently handle read and write requests for multiple memory ranks. It allocates write requests to different slots based on the target memory rank and adjusts the number of slots available for a given memory rank during a write turn to improve write efficiency. Additionally, the circuit determines the number of rank switches within a read turn based on whether specific quality-of-service requirements associated with the read requests are being met.
- Efficient memory control circuit for handling read and write requests for multiple memory ranks
- Allocates write requests to different slots based on target memory rank
- Adjusts number of slots available for a memory rank during a write turn to improve efficiency
- Determines number of rank switches within a read turn based on quality-of-service requirements
Potential Applications
The technology described in this patent application could be applied in various memory-intensive systems such as servers, data centers, and high-performance computing environments.
Problems Solved
1. Efficient allocation of write requests to different memory ranks 2. Improved write efficiency by adjusting the number of slots available for a given memory rank
Benefits
1. Enhanced memory control efficiency 2. Improved overall system performance 3. Better quality-of-service management for read requests
Potential Commercial Applications
Optimizing memory control circuits for improved performance in servers, data centers, and high-performance computing systems.
Possible Prior Art
One possible prior art could be memory control circuits that allocate read and write requests to different memory ranks but do not dynamically adjust the number of slots available for a given memory rank during a write turn.
Unanswered Questions
How does the memory control circuit handle conflicting read and write requests for the same memory rank?
The patent application does not provide specific details on how the circuit resolves conflicts between read and write requests targeting the same memory rank.
What impact does the adjustment of slots during a write turn have on overall system latency?
The patent application does not address the potential impact of dynamically adjusting the number of slots available for a given memory rank during a write turn on system latency.
Original Abstract Submitted
A memory control circuit coupled to multiple memory ranks may receive read and write requests for a different ranks of the multiple memory ranks. The memory control may allocate write requests to different slots based on the write requests target memory rank, and may adjust the number of slots available for a given memory rank during a write turn to improve write efficiency. The memory control circuit may also determine a number of ranks switches within a read turn based on whether a particular quality-of-service requirement associated with the read requests is being satisfied.
