18469609. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18469609 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Simplified Explanation
The semiconductor package described in the patent application includes a first semiconductor chip with a support structure, a second semiconductor chip stacked on top with a smaller width, and an insulating adhesive layer covering the support structure.
- First semiconductor chip with support structure
- Second semiconductor chip stacked with smaller width
- Insulating adhesive layer covering support structure
Potential Applications
The technology described in the patent application could be used in various electronic devices such as smartphones, tablets, and computers.
Problems Solved
This technology helps in reducing the size of semiconductor packages while providing insulation and support between stacked chips.
Benefits
- Improved space efficiency - Enhanced thermal performance - Increased reliability of semiconductor packages
Potential Commercial Applications
Optimizing semiconductor packages for smaller electronic devices like wearables and IoT devices.
Possible Prior Art
One possible prior art could be the use of insulating adhesive layers in semiconductor packaging to provide electrical insulation and mechanical support between stacked chips.
Unanswered Questions
How does the size reduction of the semiconductor package impact overall device performance?
The article does not provide information on the potential impact of size reduction on device performance.
Are there any limitations to the use of insulating adhesive layers in semiconductor packaging?
The article does not discuss any limitations or challenges associated with the use of insulating adhesive layers in semiconductor packaging.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip including a support structure extending away from a top surface thereof, a second semiconductor chip stacked on the first semiconductor chip, having a horizontal width that is less than that of the first semiconductor chip, and having an edge horizontally spaced apart from that of the first semiconductor chip in a plan view, and an insulating adhesive layer between the first semiconductor chip and the second semiconductor chip that extends away from between the first semiconductor chip and the second semiconductor chip to cover the support structure. In a plan view, the support structure is horizontally spaced apart from the edge of the second semiconductor chip and an edge of the insulating adhesive layer.
