18469505. COMPACT LOGIC CELLS USING FULL BACKSIDE CONNECTIVITY (QUALCOMM Incorporated)
Contents
COMPACT LOGIC CELLS USING FULL BACKSIDE CONNECTIVITY
Organization Name
Inventor(s)
Shreesh Narasimha of Charlotte NC US
Deepak Sharma of San Diego CA US
COMPACT LOGIC CELLS USING FULL BACKSIDE CONNECTIVITY
This abstract first appeared for US patent application 18469505 titled 'COMPACT LOGIC CELLS USING FULL BACKSIDE CONNECTIVITY
Original Abstract Submitted
Compact logic cells using full backside connectivity are disclosed. In an aspect, a semiconductor device comprises a plurality of integrated circuit cells comprising: gates separated by source/drain (S/D) structures and comprising at least one channel extending through a metal structure and connecting adjacent S/D structures to each other, at least one gate forming a gate-all-around field effect transistor; an FS contact electrically connecting to an S/D structure; an FS contact electrically connecting to a gate; a frontside (FS) inter-layer dielectric (ILD) on the gates and S/D structures; FS metal zero interconnects disposed on the FS-ILD, one being electrically connected to an FS contact; a BS contact electrically connecting to an S/D structure; a BS contact electrically connecting to a gate; a backside (BS) ILD disposed on the gates and S/D structures; and BS metal zero interconnects disposed on the BS-ILD, one being electrically connected to a BS contact.
