18468992. SEMICONDUCTOR PACKAGES simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGES
SEMICONDUCTOR PACKAGES
Organization Name
Inventor(s)
Myung Sam Kang of Suwon-si (KR)
SEMICONDUCTOR PACKAGES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18468992 titled 'SEMICONDUCTOR PACKAGES
Simplified Explanation
The semiconductor package described in the abstract includes a glass core, redistribution layers, semiconductor chips, and connection modules for electrical connections between the chips.
- The semiconductor package includes a first redistribution layer with a conductive pattern, a connection module on the upper surface of the first redistribution layer, a glass core surrounding the connection module, a through via in the glass core, a second insulating layer with a portion in the through via, a second redistribution layer with a via pad, and two semiconductor chips on the upper surface of the second redistribution layer connected through the connection module.
Potential Applications
This technology can be applied in various electronic devices such as smartphones, tablets, laptops, and other consumer electronics requiring compact and efficient semiconductor packaging solutions.
Problems Solved
1. Improved electrical connections between semiconductor chips. 2. Enhanced reliability and performance of semiconductor packages.
Benefits
1. Higher electrical connectivity. 2. Increased reliability and durability. 3. Space-saving design for compact electronic devices.
Potential Commercial Applications
Optimized Semiconductor Package Design for Enhanced Performance and Reliability
Possible Prior Art
There may be prior art related to semiconductor packaging technologies involving glass cores, redistribution layers, and through vias for electrical connections between semiconductor chips.
What are the potential manufacturing challenges for implementing this technology at scale?
Manufacturing challenges could include ensuring the precise alignment of the semiconductor chips on the redistribution layers, maintaining the integrity of the through vias in the glass core during the packaging process, and optimizing the electrical connections between the chips through the connection modules.
How does this technology compare to existing semiconductor packaging solutions in terms of cost-effectiveness?
This technology may offer cost-effectiveness in terms of improved reliability and performance, potentially reducing the need for frequent maintenance or replacements of electronic devices due to semiconductor package failures. However, the initial manufacturing costs and complexity of the process may need to be evaluated for overall cost-effectiveness compared to existing solutions.
Original Abstract Submitted
A semiconductor package comprises a first redistribution layer including a first conductive pattern; a connection module on an upper surface of the first redistribution layer; a glass core extending around the connection module on the upper surface of the first redistribution layer; a through via extended in the glass core; a second insulating layer on the glass core, wherein a portion of the second insulating layer is in the through via; a second redistribution layer on an upper surface of the glass core, wherein the second redistribution layer includes a via pad; and a first semiconductor chip and a second semiconductor chip space apart from each other on an upper surface of the second redistribution layer, wherein the via pad is in contact with the through via, and wherein the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the connection module.
