18468630. ENHANCED INPUT OF MACHINE-LEARNING ACCELERATOR ACTIVATIONS simplified abstract (Google LLC)
Contents
ENHANCED INPUT OF MACHINE-LEARNING ACCELERATOR ACTIVATIONS
Organization Name
Inventor(s)
Lukasz Lew of Sunnyvale CA (US)
Wren Romano of Mountain View CA (US)
ENHANCED INPUT OF MACHINE-LEARNING ACCELERATOR ACTIVATIONS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18468630 titled 'ENHANCED INPUT OF MACHINE-LEARNING ACCELERATOR ACTIVATIONS
The patent application describes methods, systems, and apparatus for scheduling operations on a machine-learning accelerator with multiple tiles.
- The apparatus includes a processor with multiple tiles and scheduling circuitry.
- The scheduling circuitry selects input activations for each tile from an activation line or a delay register for the activation line.
Potential Applications:
- Machine learning accelerators
- Artificial intelligence systems
- Data processing applications
Problems Solved:
- Efficient scheduling of operations on machine-learning accelerators
- Optimizing performance of multiple tiles in a processor
Benefits:
- Improved efficiency in processing operations
- Enhanced performance of machine-learning accelerators
Commercial Applications:
- Semiconductor industry for developing advanced processors
- Technology companies for enhancing AI systems
Prior Art:
- Researchers in the field of machine learning accelerators
- Semiconductor companies working on processor optimization
Frequently Updated Research:
- Latest advancements in machine learning accelerator technology
- Updates on scheduling algorithms for processors
Questions about the technology: 1. How does the scheduling circuitry optimize the selection of input activations for each tile? 2. What are the key differences between selecting input activations from an activation line versus a delay register?
Original Abstract Submitted
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for scheduling operations on a machine-learning accelerator having multiple tiles. The apparatus includes a processor having a plurality of tiles and scheduling circuitry that is configured to select a respective input activation for each tile of the plurality of tiles from either an activation line for the tile or a delay register for the activation line.
