18468030. SILICON CARBIDE SINGLE CRYSTAL INGOT, SILICON CARBIDE WAFER, AND METHOD FOR MANUFACTURING SILICON CARBIDE SINGLE CRYSTAL simplified abstract (TOYOTA JIDOSHA KABUSHIKI KAISHA)

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SILICON CARBIDE SINGLE CRYSTAL INGOT, SILICON CARBIDE WAFER, AND METHOD FOR MANUFACTURING SILICON CARBIDE SINGLE CRYSTAL

Organization Name

TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor(s)

Kiyoshi Betsuyaku of Tokyo (JP)

Norihiro Hoshino of Tokyo (JP)

Isaho Kamata of Tokyo (JP)

Hidekazu Tsuchida of Tokyo (JP)

Takeshi Okamoto of Nisshin-shi (JP)

Takahiro Kanda of Nisshin-shi (JP)

SILICON CARBIDE SINGLE CRYSTAL INGOT, SILICON CARBIDE WAFER, AND METHOD FOR MANUFACTURING SILICON CARBIDE SINGLE CRYSTAL - A simplified explanation of the abstract

This abstract first appeared for US patent application 18468030 titled 'SILICON CARBIDE SINGLE CRYSTAL INGOT, SILICON CARBIDE WAFER, AND METHOD FOR MANUFACTURING SILICON CARBIDE SINGLE CRYSTAL

Simplified Explanation

The method described in the patent application focuses on manufacturing a silicon carbide single crystal with reduced dislocation defects. By controlling the temperature gradient during crystal growth and optimizing the area of high shear stress regions, the conversion of threading edge dislocations into prismatic plane dislocations and basal plane dislocations is suppressed.

  • Explanation of the patent:
 * Silicon carbide single crystal grown on a seed substrate with controlled temperature gradient.
 * Area of high shear stress regions minimized to reduce dislocation defects.
 * Conversion of threading edge dislocations into prismatic plane dislocations and basal plane dislocations suppressed.
  • Potential applications of this technology:
 * High-performance electronic devices.
 * Power electronics.
 * High-temperature applications.
  • Problems solved by this technology:
 * Reduction of dislocation defects in silicon carbide single crystals.
 * Improved crystal quality for electronic and high-temperature applications.
  • Benefits of this technology:
 * Enhanced performance and reliability of electronic devices.
 * Increased efficiency in power electronics.
 * Extended lifespan in high-temperature environments.
  • Potential commercial applications of this technology:
 * Semiconductor industry.
 * Power electronics manufacturers.
 * High-temperature equipment suppliers.
  • Possible prior art:
 * Previous methods for growing silicon carbide single crystals with varying success rates in reducing dislocation defects.
  1. Unanswered Questions
    1. How does this method compare to existing techniques for reducing dislocation defects in silicon carbide single crystals?

The article does not provide a direct comparison with other existing techniques for reducing dislocation defects in silicon carbide single crystals. Further research or experimentation may be needed to determine the effectiveness of this method compared to others.

    1. What are the specific temperature gradient values used in the method, and how do they contribute to reducing dislocation defects?

The article mentions controlling the temperature gradient during crystal growth but does not specify the exact values used or how they directly impact the reduction of dislocation defects. Additional information on the specific temperature gradient values and their effects would provide a more comprehensive understanding of the method.


Original Abstract Submitted

Provided are a method for manufacturing a silicon carbide single crystal, which can suppress conversion of threading edge dislocations into prismatic plane dislocations and conversion of the prismatic plane dislocations into basal plane dislocations; and a silicon carbide single crystal ingot and a silicon carbide wafer, in which conversion from threading edge dislocations into prismatic plane dislocations and conversion from the prismatic plane dislocations into basal plane dislocations have been suppressed. A silicon carbide single crystal is grown on the surface of a seed substrate by a gas method so that a temperature gradient in the radial direction of the seed substrate takes a predetermined value or lower during the growth. The area of regions T to T, where regions R to R of a basal plane whose shear stresses exceed critical resolved shear stress, and regions S to S of a prismatic plane whose shear stresses exceed critical resolved shear stress overlap, is less than a half of the area of a crystal growth surface. Furthermore, the area of the regions T to T is smaller than the area of regions V to V where a region R of the basal plane whose shear stress does not exceed the critical resolved shear stress overlaps the regions S to S