18460509. SEMICONDUCTOR MEMORY DEVICE simplified abstract (Kioxia Corporation)

SEMICONDUCTOR MEMORY DEVICE

Organization Name

Kioxia Corporation

Inventor(s)

Hiroshi Kanno of Yokkaichi Mie (JP)

SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18460509 titled 'SEMICONDUCTOR MEMORY DEVICE

Simplified Explanation

The semiconductor memory device described in the patent application includes multiple wiring layers, memory pillars, and insulating members to improve memory storage and retrieval capabilities.

• The device has a first wiring layer above a first semiconductor layer and a second wiring layer above the first semiconductor layer but spaced from the first wiring layer.
• Memory pillars extend through the wiring layers to enhance memory capacity.
• An insulating member between the wiring layers includes a conductor, insulator, and multiple insulators arranged in different directions to optimize memory performance.

Potential Applications

The technology described in this patent application could be applied in various electronic devices requiring high-density memory storage, such as smartphones, tablets, and computers.

Problems Solved

This innovation addresses the challenge of increasing memory capacity in semiconductor devices while maintaining efficient data retrieval speeds and minimizing power consumption.

Benefits

The benefits of this technology include improved memory performance, higher storage capacity, and enhanced overall efficiency in semiconductor memory devices.

Potential Commercial Applications

The technology could be valuable for semiconductor manufacturers looking to develop next-generation memory devices with increased capacity and improved performance.

Possible Prior Art

One possible prior art in this field is the use of multiple wiring layers in semiconductor memory devices to enhance memory storage capabilities. However, the specific configuration and arrangement of memory pillars and insulating members as described in this patent application may be a novel approach.

How does this technology compare to existing memory storage solutions on the market?

This article does not provide a direct comparison between this technology and other memory storage solutions currently available.

What are the potential challenges in implementing this technology on a large scale for commercial production?

The article does not address the potential obstacles or difficulties that may arise when scaling up the production of semiconductor memory devices using this technology.

Original Abstract Submitted

According to one embodiment, a semiconductor memory device includes a first wiring layer above a first semiconductor layer in a first direction and a second wiring layer above the first semiconductor layer and spaced from the first wiring layer in a second direction. A first memory pillar extends through the first wiring layer. A second memory pillar extends through the second wiring layer. A member is between the first and second wiring layers in the second direction and includes a first conductor contacting the first semiconductor layer, a first insulator between the wiring layers and the first conductor, and a plurality of second insulators arranged along a third direction and between the first conductor and the first semiconductor layer in the first direction.