18459745. STORAGE DEVICE simplified abstract (Kioxia Corporation)

STORAGE DEVICE

Organization Name

Kioxia Corporation

Inventor(s)

Hiroaki Kosako of Yokkaichi Mie (JP)

Kota Nishikawa of Zama Kanagawa (JP)

Kenrou Kikuchi of Fujisawa Kanagawa (JP)

STORAGE DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18459745 titled 'STORAGE DEVICE

Simplified Explanation

The abstract describes a patent application related to a memory cell structure with specific voltage applications during different periods. Here is a simplified explanation of the abstract:

• A first select transistor is connected to a first wiring.
• A first memory cell transistor and a second memory cell transistor are connected in series between the first select transistor and a second select transistor.
• A first word line is connected to the first memory cell transistor, and a second word line is connected to the second memory cell transistor.
• Different voltages are applied to the word lines and wiring during different periods.

1. 1. 1. Potential Applications:

- Memory storage devices - Integrated circuits

1. 1. 1. Problems Solved:

- Efficient memory cell structure - Controlled voltage applications

1. 1. 1. Benefits:

- Improved memory cell performance - Enhanced data storage capabilities

1. 1. 1. Potential Commercial Applications:
         1. Optimized Memory Cell Structure for Enhanced Performance

1. 1. 1. Possible Prior Art:

There may be prior art related to memory cell structures and voltage applications in memory devices.

1. 1. 1. 1. Unanswered Questions:
         2. How does this memory cell structure compare to existing designs in terms of performance and efficiency?

This article does not provide a direct comparison with existing memory cell structures.

1. 1. 1. 1. What are the specific voltage ranges used in the different periods, and how do they impact the overall functionality of the memory cell structure?

The article does not delve into the specific voltage ranges and their detailed effects on the memory cell structure.

Original Abstract Submitted

A first select transistor is connected to a first wiring. A first memory cell transistor and a second memory cell transistor are connected in series between the first select transistor and a second select transistor. A first word line is connected to the first memory cell transistor. A second word line is connected to the second memory cell transistor. During a first period in which the first voltage is applied to the first wiring, a second voltage lower than a first voltage is applied in parallel to the first word line and the second word line. During a second period in which a third voltage higher than the first voltage is applied to the first wiring, the second voltage is applied to the first word line, and a fourth voltage higher than the second voltage and lower than the third voltage is applied to the second word line. During a third period in which the third voltage is applied to the first wiring, the fourth voltage is applied to the first word line, and the second voltage is applied to the second word line.