18456248. MEMORY SYSTEM AND CONTROL METHOD simplified abstract (Kioxia Corporation)
Contents
- 1 MEMORY SYSTEM AND CONTROL METHOD
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY SYSTEM AND CONTROL METHOD - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
MEMORY SYSTEM AND CONTROL METHOD
Organization Name
Inventor(s)
Mariko Matsumoto of Kawasaki Kanagawa (JP)
MEMORY SYSTEM AND CONTROL METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 18456248 titled 'MEMORY SYSTEM AND CONTROL METHOD
Simplified Explanation
The memory system described in the patent application includes a memory, a control circuit, and an interface circuit. The control circuit transitions between different states based on input signals received from the interface circuit.
- The interface circuit has two terminals - one for receiving a clock signal and another for receiving a data signal.
- The control circuit transitions to a second state upon receiving a data signal and to a third state upon receiving a clock signal.
- In the second state, the control circuit initializes a first mode of operation using an internally generated clock or operates in the first mode, transitioning to the third state upon receiving the clock signal.
- In the third state, the control circuit transitions to a fourth state upon receiving a data signal.
- In the fourth state, the control circuit initializes a second mode of operation using the clock signal or operates in the second mode.
Potential Applications
This technology could be applied in various memory systems, such as computer RAM, to improve performance and efficiency.
Problems Solved
This technology helps in efficiently managing memory operations and transitions between different modes of operation.
Benefits
The memory system offers improved control and flexibility in managing memory operations, leading to enhanced performance and reliability.
Potential Commercial Applications
The technology could find applications in computer systems, servers, and other electronic devices requiring efficient memory management.
Possible Prior Art
One possible prior art could be memory systems with basic control circuits that do not have the capability to transition between different modes of operation based on input signals.
Unanswered Questions
How does this technology compare to existing memory management systems in terms of speed and efficiency?
The article does not provide a direct comparison with existing memory management systems to evaluate the speed and efficiency improvements offered by this technology.
Are there any limitations or constraints in implementing this memory system in real-world applications?
The article does not address any potential limitations or constraints that may arise when implementing this memory system in practical electronic devices.
Original Abstract Submitted
A memory system includes a memory, a control circuit, and an interface circuit. The interface circuit includes a first terminal capable of receiving a first clock supplied from an outside, and a second terminal capable of receiving a first signal. When in a first state, the control circuit transitions to a second state in response to input of a first signal, and to a third state in response to input of the first clock. When in the second state, the control circuit executes initialization processing of a first mode for an operation based on an internally generated second clock or is in an operable state in the first mode, and ends the operable state in the first mode in response to input of the first clock and transitions to the third state. When in the third state, the control circuit transitions to a fourth state in response to input of the first signal. When in the fourth state, the control circuit executes initialization processing of a second mode for an operation based on the first clock or is in an operable state in the second mode.
