18444379. APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER simplified abstract (Intel Corporation)

APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER

Organization Name

Intel Corporation

Inventor(s)

Michelle M. Wigton of Timnath CO (US)

Kambiz R. Munshi of Westford MA (US)

Zhongyao Linda Gu of Acton MA (US)

Mohammad M. Rashid of San Jose CA (US)

Victor Lau of Marlborough MA (US)

Jing Ling of Milpitas CA (US)

APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER - A simplified explanation of the abstract

This abstract first appeared for US patent application 18444379 titled 'APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER

Simplified Explanation

Memory power consumption is reduced in a memory controller by disabling certain circuitry when inactive, without increasing latency of memory read access.

Key Features and Innovation

• Reducing power consumption in a memory controller without impacting memory read access latency.
• Disabling receiver bias circuitry and clock network in the PHY when inactive to save power.
• Sending command-based signals from the memory controller to enable the PHY to transition from a low power state to an active power state.
• Using an early command indication signal and a read indication signal to activate the clock network and receiver bias circuitry in the PHY.

Potential Applications

This technology can be applied in various electronic devices that use memory controllers, such as smartphones, tablets, laptops, and other computing devices.

Problems Solved

• Reducing power consumption in memory controllers without sacrificing performance.
• Efficiently managing power usage in electronic devices to prolong battery life.

Benefits

• Extended battery life in electronic devices.
• Improved energy efficiency in memory controllers.
• Enhanced overall performance of electronic devices.

Commercial Applications

Optimizing Power Consumption in Electronic Devices

This technology can be utilized in the development of energy-efficient electronic devices, leading to longer battery life and improved user experience.

Prior Art

There may be prior art related to power management techniques in memory controllers and PHYs that could provide additional insights into similar innovations in the field.

Frequently Updated Research

Research on power management techniques in memory controllers and PHYs is continuously evolving to enhance energy efficiency in electronic devices.

Questions about Memory Power Consumption

How does disabling receiver bias circuitry and clock network in the PHY reduce power consumption in memory controllers?

Disabling these components when inactive helps save power without affecting memory read access latency.

What are the potential applications of this technology beyond memory controllers?

This technology can be applied in various electronic devices to improve energy efficiency and prolong battery life.

Original Abstract Submitted

Memory power consumption is reduced without increasing latency of memory read access. When inactive, power consumption is reduced in a PHY in a memory controller by disabling receiver bias circuitry and a clock network in the PHY. The memory controller sends two command-based signals to the PHY to enable the PHY to enable the receiver bias circuitry and the clock network in the PHY to transition the memory from a low power state to an active power state prior to or at the time of receiving command from the memory controller. A first command-based signal is an early command indication signal that is sent before any command. The second command-based signal is a read indication signal that is sent synchronous with every read command. Upon receiving these signals, the PHY enables the clock network and receiver bias circuitry.