18437961. FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING PRE-SPACER DEPOSITION CUT GATES simplified abstract (Intel Corporation)

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING PRE-SPACER DEPOSITION CUT GATES

Organization Name

Intel Corporation

Inventor(s)

Leonard P. Guler of Hillsboro OR (US)

Michael K. Harper of Hillsboro OR (US)

William Hsu of Hillsboro OR (US)

Biswajeet Guha of Hillsboro OR (US)

Tahir Ghani of Portland OR (US)

Niels Zussblatt of Hillsboro OR (US)

Jeffrey Miles Tan of Hillsboro OR (US)

Benjamin Kriegel of Portland OR (US)

Mohit K. Haran of Hillsboro OR (US)

Reken Patel of Portland OR (US)

Oleg Golonzka of Beaverton OR (US)

Mohammad Hasan of Aloha OR (US)

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING PRE-SPACER DEPOSITION CUT GATES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18437961 titled 'FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING PRE-SPACER DEPOSITION CUT GATES

Simplified Explanation

The abstract describes gate-all-around integrated circuit structures with pre-spacer-deposition cut gates. The structure includes two vertical arrangements of horizontal nanowires with gate stacks and a dielectric structure forming gate spacers and filling gaps between the gate stacks.

• Gate-all-around integrated circuit structures with pre-spacer-deposition cut gates:

   * Includes vertical arrangements of horizontal nanowires
   * Features gate stacks over the nanowire arrangements
   * Utilizes a dielectric structure to form gate spacers and fill gaps between gate stacks

Potential Applications

The technology can be applied in:

• Nanoelectronics
• Semiconductor industry

Problems Solved

This technology addresses:

• Improving transistor performance
• Enhancing integration density

Benefits

The benefits of this technology include:

• Increased efficiency
• Enhanced functionality

Potential Commercial Applications

The potential commercial applications of this technology can be seen in:

• Advanced computing devices
• High-performance electronics

Possible Prior Art

One possible prior art for this technology could be:

• FinFET transistor structures

Unanswered Questions

How does this technology impact power consumption in integrated circuits?

This article does not delve into the specific effects of this technology on power consumption in integrated circuits.

What are the potential challenges in scaling this technology for mass production?

The article does not address the potential challenges that may arise in scaling this technology for mass production.

Original Abstract Submitted

Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.