18437158. ELECTRONIC DEVICE FOR UPDATING FRAME ERROR RATE OF LINK AND OPERATION METHOD OF ELECTRONIC DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 ELECTRONIC DEVICE FOR UPDATING FRAME ERROR RATE OF LINK AND OPERATION METHOD OF ELECTRONIC DEVICE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 ELECTRONIC DEVICE FOR UPDATING FRAME ERROR RATE OF LINK AND OPERATION METHOD OF ELECTRONIC DEVICE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
ELECTRONIC DEVICE FOR UPDATING FRAME ERROR RATE OF LINK AND OPERATION METHOD OF ELECTRONIC DEVICE
Organization Name
Inventor(s)
Changmok Yang of Suwon-si (KR)
Chounjong Nam of Suwon-si (KR)
Mincheol Jeong of Suwon-si, Gyeonggi-do (KR)
ELECTRONIC DEVICE FOR UPDATING FRAME ERROR RATE OF LINK AND OPERATION METHOD OF ELECTRONIC DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18437158 titled 'ELECTRONIC DEVICE FOR UPDATING FRAME ERROR RATE OF LINK AND OPERATION METHOD OF ELECTRONIC DEVICE
Simplified Explanation
The embodiment of an electronic device described in the patent application involves a communication circuit, a memory for storing mapping data, and a processor. The processor is configured to identify a suitable link for transmitting packets based on predetermined criteria, transmit or receive packets through the identified link, analyze frame error rates, and update mapping data accordingly.
- Communication circuit for data transmission/reception through multiple links
- Memory for storing mapping data of data rates and frame error rates for links
- Processor to identify optimal link for packet transmission, transmit/receive packets, analyze frame error rates, and update mapping data
Potential Applications
This technology could be applied in various communication systems where optimizing data transmission reliability and efficiency is crucial, such as in wireless networks, satellite communications, and industrial automation systems.
Problems Solved
This technology addresses the challenge of efficiently managing data transmission across multiple links by dynamically selecting the most suitable link based on performance metrics, ultimately improving overall system reliability and performance.
Benefits
The benefits of this technology include enhanced data transmission reliability, improved network efficiency, reduced packet loss, and optimized utilization of communication links, leading to better overall system performance.
Potential Commercial Applications
Potential commercial applications of this technology include telecommunications infrastructure, IoT devices, autonomous vehicles, and any system requiring reliable and efficient data transmission across multiple links.
Possible Prior Art
One possible prior art could be systems that utilize similar methods for optimizing data transmission across multiple links, such as load balancing algorithms in network routers or adaptive modulation and coding techniques in wireless communication systems.
What is the impact of this technology on data transmission efficiency in wireless networks?
This technology significantly improves data transmission efficiency in wireless networks by dynamically selecting the optimal link for packet transmission based on performance metrics, reducing packet loss, and enhancing overall network reliability.
How does this innovation contribute to the advancement of communication systems?
This innovation contributes to the advancement of communication systems by providing a more intelligent and adaptive approach to data transmission, optimizing link utilization, and improving overall system performance and reliability.
Original Abstract Submitted
An embodiment of an electronic device according to the present disclosure may comprise: a communication circuit for transmitting or receiving data through a plurality of links; a memory for storing mapping data in which data rates and frame error rates for the plurality of links are mapped; and a processor operatively connected to the communication circuit and the memory, wherein the processor is configured to: in response to a request for transmitting a packet corresponding to a first type, identify a link, through which the number of packets less than a predesignated value have been transmitted or received, from among the plurality of links; transmit or receive a plurality of packets corresponding to a second type through the identified link; identify frame error rates for the plurality of packets corresponding to the second type; and update the mapping data on the basis of the identified frame error rates.
