18435993. FPGA Specialist Processing Block for Machine Learning simplified abstract (Intel Corporation)

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FPGA Specialist Processing Block for Machine Learning

Organization Name

Intel Corporation

Inventor(s)

Martin Langhammer of Alderbury (GB)

Dongdong Chen of San Jose CA (US)

Jason R. Bergendahl of Cupertino CA (US)

FPGA Specialist Processing Block for Machine Learning - A simplified explanation of the abstract

This abstract first appeared for US patent application 18435993 titled 'FPGA Specialist Processing Block for Machine Learning

Simplified Explanation

The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

  • The DSP block includes multiple columns of weight registers.
  • The DSP block has inputs for receiving two sets of values.
  • The first set of values is stored in the weight registers.
  • The DSP block contains multiple multipliers for multiplying corresponding values from the two sets simultaneously.

Potential Applications

This technology could be applied in:

  • Digital signal processing systems
  • Image and video processing applications
  • Communication systems

Problems Solved

This technology helps in:

  • Efficiently processing multiple sets of values simultaneously
  • Improving the speed and accuracy of signal processing tasks

Benefits

The benefits of this technology include:

  • Faster processing of data
  • Increased efficiency in signal processing
  • Enhanced performance in various applications

Potential Commercial Applications

A potential commercial application of this technology could be in:

  • High-speed data processing systems
  • Telecommunication equipment
  • Image and video processing devices

Possible Prior Art

One possible prior art for this technology could be:

  • Existing digital signal processing blocks with single sets of inputs and weight registers.

Unanswered Questions

How does this technology compare to existing DSP blocks in terms of speed and efficiency?

The article does not provide a direct comparison with existing DSP blocks in terms of speed and efficiency.

Are there any limitations to the number of values that can be processed simultaneously by this DSP block?

The article does not mention any limitations on the number of values that can be processed simultaneously by this DSP block.


Original Abstract Submitted

The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.