18435609. DUAL METAL SILICIDE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION simplified abstract (Intel Corporation)

DUAL METAL SILICIDE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Organization Name

Intel Corporation

Inventor(s)

Jeffrey S. Leib of Beaverton OR (US)

Srijit Mukherjee of Portland OR (US)

Vinay Bhagwat of Hillsboro OR (US)

Michael L. Hattendorf of Portland OR (US)

Christopher P. Auth of Portland OR (US)

DUAL METAL SILICIDE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18435609 titled 'DUAL METAL SILICIDE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Simplified Explanation

The patent application is related to advanced integrated circuit structure fabrication, specifically focusing on the 10 nanometer node and smaller integrated circuit structures. The structure includes P-type and N-type semiconductor devices with metal silicide layers on the source or drain regions.

• P-type and N-type semiconductor devices are included in the integrated circuit structure.
• Metal silicide layers are directly on the semiconductor source or drain regions.
• The first metal silicide layer contains a metal species not found in the second metal silicide layer.

Potential Applications

This technology can be applied in the manufacturing of advanced integrated circuits for various electronic devices such as smartphones, computers, and IoT devices.

Problems Solved

This technology helps in achieving smaller integrated circuit structures with improved performance and efficiency, meeting the demands of modern electronic devices.

Benefits

The use of metal silicide layers enhances the conductivity and reliability of the semiconductor devices, leading to better overall performance of the integrated circuits.

Potential Commercial Applications

The technology can be utilized by semiconductor manufacturers to produce high-performance integrated circuits for consumer electronics, automotive applications, and industrial equipment.

Possible Prior Art

One possible prior art could be the use of metal silicide layers in semiconductor devices to improve conductivity and performance. However, the specific configuration and composition of the metal silicide layers in this patent application may be novel and inventive.

How does this technology compare to existing methods in terms of cost-effectiveness?

The cost-effectiveness of implementing metal silicide layers in semiconductor devices compared to other materials or techniques is not addressed in the patent application. Further research or analysis may be needed to determine the economic viability of this technology.

What impact does this technology have on the overall power consumption of integrated circuits?

The potential effects of using metal silicide layers on power consumption in integrated circuits are not discussed in the patent application. Additional studies or experiments could provide insights into the energy efficiency of this technology.

Original Abstract Submitted

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.