18435197. STACKED SEMICONDUCTOR DEVICE TEST CIRCUITS AND METHODS OF USE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

STACKED SEMICONDUCTOR DEVICE TEST CIRCUITS AND METHODS OF USE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Jen-Yuan Chang of Hsinchu City (TW)

STACKED SEMICONDUCTOR DEVICE TEST CIRCUITS AND METHODS OF USE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18435197 titled 'STACKED SEMICONDUCTOR DEVICE TEST CIRCUITS AND METHODS OF USE

Simplified Explanation

The abstract describes a patent application for a control circuit included in a stacked semiconductor device that allows for selective blocking of a die-to-die interconnect to isolate individual dies for independent testing after bonding.

• The control circuit is integrated into the first die of a stacked semiconductor device.
• The control circuit is connected to a transistor that can block the die-to-die interconnect.
• The transistor is controlled by the control circuit to selectively isolate the first die and a second die for independent testing.
• This technology enables more effective identification and isolation of defects in individual dies, improving the rework or repair process for the stacked semiconductor device.

Potential Applications

The technology described in the patent application could be applied in the semiconductor manufacturing industry for testing and repairing stacked semiconductor devices.

Problems Solved

This technology addresses the challenge of identifying and isolating defects in individual dies of a stacked semiconductor device, which can be difficult without the ability to independently test each die.

Benefits

The ability to selectively block die-to-die interconnects for independent testing can lead to more efficient defect identification and repair processes, ultimately improving the overall quality of stacked semiconductor devices.

Potential Commercial Applications

One potential commercial application of this technology could be in the production of high-density memory modules where individual dies need to be tested and repaired before final assembly.

Possible Prior Art

One possible prior art for this technology could be the use of test structures within semiconductor devices to isolate and test individual components. However, the specific method of selectively blocking die-to-die interconnects for independent testing may be a novel innovation.

How does this technology impact the overall yield of stacked semiconductor devices?

The technology's ability to improve defect identification and repair processes may lead to higher overall yields in the production of stacked semiconductor devices.

What are the potential cost implications of implementing this technology in semiconductor manufacturing?

The cost of integrating the control circuit and transistor into each die of a stacked semiconductor device, as well as the additional testing steps required, could impact the overall production costs of the devices.

Original Abstract Submitted

A control circuit is included in a first die of a stacked semiconductor device. The first die further includes a transistor that is electrically connected to the control circuit. The transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. In this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. This may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.