18435140. Transistor Gate Structure and Method of Forming simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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Transistor Gate Structure and Method of Forming

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Hsin-Yi Lee of Hsinchu (TW)

Cheng-Lung Hung of Hsinchu (TW)

Chi On Chui of Hsinchu (TW)

Transistor Gate Structure and Method of Forming - A simplified explanation of the abstract

This abstract first appeared for US patent application 18435140 titled 'Transistor Gate Structure and Method of Forming

Simplified Explanation

The patent application describes a device with a unique structure involving nanostructures, high-k gate dielectric, and specific materials for the gate electrode.

  • The device includes a first nanostructure and a second nanostructure stacked on top of each other.
  • A high-k gate dielectric surrounds the nanostructures, with different portions on the top and bottom surfaces.
  • The gate electrode is made of a first work function metal and a tungsten layer, with the first metal filling the gap between the high-k dielectric portions.

Potential Applications

This technology could be applied in advanced semiconductor devices, such as transistors, to improve performance and efficiency.

Problems Solved

This innovation addresses the challenge of reducing leakage currents and improving gate control in nanostructured devices.

Benefits

The device structure allows for better gate control, leading to enhanced performance and lower power consumption in electronic devices.

Potential Commercial Applications

This technology could be valuable in the development of next-generation processors, memory devices, and other semiconductor products.

Possible Prior Art

Prior art may include patents or publications related to nanostructure-based transistors, high-k gate dielectrics, and gate electrode materials in semiconductor devices.

Unanswered Questions

How does this technology compare to existing transistor structures in terms of performance and power efficiency?

This article does not provide a direct comparison with existing transistor structures to evaluate performance and power efficiency.

What are the potential challenges in scaling up this technology for mass production in semiconductor manufacturing?

The article does not discuss the potential challenges in scaling up this technology for mass production in semiconductor manufacturing.


Original Abstract Submitted

A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nanostructure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.