18432923. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE simplified abstract (Mitsubishi Electric Corporation)
Contents
- 1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 How does this technology compare to existing semiconductor device structures in terms of performance and efficiency?
- 1.11 What are the specific manufacturing processes involved in creating the N buffer layer with trap levels in this semiconductor device?
- 1.12 Original Abstract Submitted
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Organization Name
Mitsubishi Electric Corporation
Inventor(s)
Katsumi Nakamura of Tokyo (JP)
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18432923 titled 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Simplified Explanation
The semiconductor device described in the abstract includes an N drift layer, a P base layer, and an N buffer layer with specific trap levels.
- N drift layer of a first conductivity type in the semiconductor substrate
- P base layer on top of the N drift layer
- N buffer layer of the first conductivity type under the N drift layer with higher impurity concentration
- N buffer layer consists of a first buffer layer without trap levels from lattice defects and a second buffer layer with two trap levels from lattice defects
Potential Applications
The technology described in this patent application could be applied in:
- Power electronics
- Semiconductor devices
- Solar cells
Problems Solved
This technology helps in:
- Improving the performance of semiconductor devices
- Reducing defects in the semiconductor substrate
- Enhancing the efficiency of power electronics
Benefits
The benefits of this technology include:
- Higher efficiency in power conversion
- Improved reliability of semiconductor devices
- Enhanced performance of solar cells
Potential Commercial Applications
The potential commercial applications of this technology could be in:
- Semiconductor manufacturing companies
- Power electronics industry
- Solar energy companies
Possible Prior Art
One possible prior art for this technology could be:
- Previous patents related to semiconductor device structures with buffer layers
Unanswered Questions
How does this technology compare to existing semiconductor device structures in terms of performance and efficiency?
This article does not provide a direct comparison with existing semiconductor device structures in terms of performance and efficiency. Further research or testing may be needed to determine the advantages of this technology over existing ones.
What are the specific manufacturing processes involved in creating the N buffer layer with trap levels in this semiconductor device?
The article does not delve into the specific manufacturing processes involved in creating the N buffer layer with trap levels. Additional information or documentation from the patent application may be required to understand the manufacturing techniques used in this technology.
Original Abstract Submitted
A semiconductor device includes: an N drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N drift layer; and an N buffer layer of the first conductivity type formed under the N drift layer and higher in peak impurity concentration than the N drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.
