18432326. MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)

MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES

Organization Name

Micron Technology, Inc.

Inventor(s)

Vamsi Pavan Rayaprolu of Santa Clara CA (US)

Mustafa N. Kaynak of San Diego CA (US)

Sivagnanam Parthasarathy of Carlsbad CA (US)

Patrick Khayat of San Diego CA (US)

Sampath Ratnam of San Jose CA (US)

Kishore Kumar Muchherla of Fremont CA (US)

Jiangang Wu of Milpitas CA (US)

James Fitzpatrick of Laguna Niguel CA (US)

MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18432326 titled 'MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES

Simplified Explanation

The abstract describes a patent application for a system and method involving a memory device and a processing device. The processing device performs operations such as data integrity checks on memory cells, error handling operations, and copying corrected data to another set of memory cells with a higher storage capacity.

• The patent application involves a system with a memory device and a processing device.
• The processing device conducts data integrity checks on memory cells storing a specific number of bits per cell.
• If the data integrity metric value meets a threshold criterion, error handling operations are performed to generate corrected data.
• The corrected data is then copied to a different set of memory cells with a higher storage capacity.

Potential Applications

This technology could be applied in data storage systems, ensuring data integrity and reliability in memory devices.

Problems Solved

This technology addresses issues related to data corruption and errors in memory storage systems, improving overall data reliability.

Benefits

The benefits of this technology include enhanced data integrity, error correction capabilities, and increased storage capacity in memory devices.

Potential Commercial Applications

A potential commercial application of this technology could be in the development of high-performance storage devices for various industries.

Possible Prior Art

One possible prior art for this technology could be existing error correction techniques in memory systems, although this specific combination of operations may be novel.

How does this technology compare to existing error correction methods in terms of efficiency and effectiveness?

This article does not provide a direct comparison between this technology and existing error correction methods. Further research or testing may be needed to evaluate the performance of this innovation.

What impact could this technology have on the cost of memory devices and data storage systems?

The article does not discuss the potential cost implications of implementing this technology. Understanding the economic impact of this innovation on the market would require additional analysis and market research.

Original Abstract Submitted

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies the threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and causing the memory device to copy data the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.