18430903. CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE simplified abstract (HUAWEI TECHNOLOGIES CO., LTD.)
Contents
- 1 CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE
Organization Name
Inventor(s)
Shanghsuan Chiang of Shenzhen (CN)
CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18430903 titled 'CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE
Simplified Explanation
The chip package structure described in the patent application includes a substrate, a first connection chip, conductive columns, a first packaging layer, a first chip, and a second chip. The first connection chip is placed on the substrate, with conductive columns located on the periphery of the first connection chip. The first packaging layer wraps the first connection chip and conductive columns, exposing their active surface and top surfaces. The first chip is placed on the first packaging layer and connected to both the conductive columns and the first connection chip. The second chip is also placed on the first packaging layer, away from the substrate, and connected to both the conductive columns and the first connection chip.
- The structure includes a substrate, first connection chip, conductive columns, first packaging layer, first chip, and second chip.
- The first connection chip is on the substrate, with conductive columns on its periphery.
- The first packaging layer wraps the first connection chip and conductive columns, exposing their surfaces.
- The first chip is connected to both the conductive columns and the first connection chip.
- The second chip is connected to both the conductive columns and the first connection chip.
Potential Applications
This chip package structure could be used in various electronic devices such as smartphones, tablets, laptops, and other portable electronics.
Problems Solved
This technology solves the problem of efficiently connecting multiple chips in a compact and reliable manner, reducing the overall size of electronic devices.
Benefits
The benefits of this technology include improved performance, reduced size, increased reliability, and potentially lower manufacturing costs.
Potential Commercial Applications
The potential commercial applications of this technology could be in the semiconductor industry, consumer electronics sector, and any other fields requiring compact and efficient chip packaging solutions.
Possible Prior Art
One possible prior art for this technology could be the use of stacked chip packages in electronic devices to save space and improve performance.
Unanswered Questions
How does this technology compare to traditional chip packaging methods?
This article does not provide a direct comparison between this chip package structure and traditional chip packaging methods.
What are the specific materials used in the construction of this chip package structure?
The article does not mention the specific materials used in the construction of this chip package structure.
Original Abstract Submitted
A chip package structure includes: a substrate, a first connection chip, conductive columns, a first packaging layer, a first chip, and a second chip. The first connection chip is disposed on the substrate. The conductive columns is disposed on the substrate and located on a periphery of the first connection chip. The first packaging layer is disposed on the substrate and wrapping the first connection chip and the conductive columns, with the active surface of the first connection chip and top surfaces of the conductive columns exposed. The first chip is disposed on the first packaging layer, and coupled to both the conductive columns and the first connection chip. The second chip is disposed on the first packaging layer and that is away from the substrate, and coupled to both the conductive columns and the first connection chip.
