18426282. STACKED SEMICONDUCTOR DEVICE simplified abstract (Micron Technology, Inc.)
Contents
STACKED SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
Yeon Seung Jung of Hwaseong (KR)
STACKED SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18426282 titled 'STACKED SEMICONDUCTOR DEVICE
Simplified Explanation:
This patent application describes a semiconductor device with two stacks of semiconductor dies staggered on a substrate, with conductive structures connecting them.
- The semiconductor device includes a substrate and two stacks of semiconductor dies.
- The first and second stacks of semiconductor dies are staggered, with the second stack partially overlapping the first.
- Each die in the first stack is vertically mounted to a die in the second stack.
- Conductive structures connect portions of the stacks beyond their footprints to electrically couple the dies.
Key Features and Innovation:
- Staggered arrangement of semiconductor dies on a substrate.
- Vertical mounting of dies from different stacks.
- Conductive structures for electrical coupling.
Potential Applications:
This technology could be used in various semiconductor devices, such as integrated circuits, memory modules, and microprocessors.
Problems Solved:
This innovation helps optimize space utilization and improve electrical connectivity in semiconductor devices.
Benefits:
- Enhanced performance and efficiency in semiconductor devices.
- Compact design for space-constrained applications.
Commercial Applications:
Potential commercial applications include consumer electronics, telecommunications equipment, and automotive electronics.
Questions about Semiconductor Device Stacking:
1. How does the staggered arrangement of semiconductor dies benefit the overall design of the device? 2. What are the advantages of vertically mounting dies from different stacks in a semiconductor device?
Original Abstract Submitted
A semiconductor device is provided that can include a substrate and a first and second stack of semiconductor dies coupled to the substrate. The first stack of semiconductor dies and the second stack of semiconductor dies are staggered such that the first stack of semiconductor dies has a first footprint and the second stack of semiconductor dies has a second footprint that partially overlaps the first footprint. The first stack of semiconductor dies and the second stack of semiconductor dies are alternated such that each semiconductor die of the first stack of semiconductor dies is vertically mounted to a respective semiconductor die of the second stack of semiconductor dies. Conductive structures extend between portions of the first and second stacks of semiconductor dies exposed beyond the second footprint and the first footprint, respectively, to electrically couple the semiconductor dies.
