18423329. DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Samsung Display Co., Ltd.)
Contents
DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
Organization Name
Inventor(s)
Hyun Eok Shin of Yongin-si (KR)
Joon Yong Park of Yongin-si (KR)
Do Keun Song of Yongin-si (KR)
Yu-Gwang Jeong of Yongin-si (KR)
DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18423329 titled 'DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
The abstract describes a display device with transistors, an insulating layer, a first electrode, a partition wall, and a common layer.
- Transistors are placed on a substrate.
- An insulating layer is on top of the transistors.
- A first electrode is connected to at least one transistor.
- A partition wall with a groove is on the insulating layer.
- A common layer is on the partition wall and the first electrode.
Potential Applications: - This technology can be used in the manufacturing of high-resolution displays for electronic devices. - It can also be applied in the development of touchscreens and flexible displays.
Problems Solved: - Provides a structure for improved display performance and durability. - Enhances the efficiency of electronic devices with display screens.
Benefits: - Increased display quality and resolution. - Enhanced durability and longevity of electronic displays.
Commercial Applications: - This technology can be utilized in the production of smartphones, tablets, laptops, and other electronic devices with display screens.
Questions about the technology: 1. How does the groove in the partition wall contribute to the functionality of the display device? 2. What specific advantages does the common layer provide in this technology?
Original Abstract Submitted
An embodiment provides a display device including transistors disposed on a substrate; an insulating layer disposed on the transistors; a first electrode disposed on the insulating layer and electrically connected to at least one of the transistors; a partition wall disposed on the insulating layer, and a common layer disposed on the partition wall and the first electrode, wherein the partition wall includes a groove, the groove has a shape having an inner width wider than an inlet width, and the common layer is disposed inside the groove.
