18423229. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
MYUNGSAM Kang of Suwon-si (KR)
JEONGSEOK Kim of Cheonan-si (KR)
KYUNG DON Mun of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18423229 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes multiple layers and components such as package substrate, interposer substrate, redistribution substrates, semiconductor chips, and connection substrate. The arrangement of these elements allows for efficient connection and communication within the package.
- Package includes package substrate, interposer substrate, redistribution substrates, semiconductor chips, and connection substrate.
- Interposer molding layer separates first and second redistribution substrates.
- Connection hole in connection substrate allows for placement of semiconductor chips.
- First semiconductor chip is placed on interposer substrate within connection hole.
- Second semiconductor chip is also on interposer substrate, spaced apart from the first chip.
- Connection semiconductor chip is located in the interposer molding layer.
Potential Applications
The technology described in this patent application could be applied in various semiconductor packaging applications, especially in high-density integrated circuits where efficient communication between different components is crucial.
Problems Solved
This technology solves the problem of optimizing space and connections within a semiconductor package, allowing for more efficient communication between different semiconductor chips.
Benefits
The benefits of this technology include improved performance, increased efficiency, and potentially reduced size of semiconductor packages.
Potential Commercial Applications
One potential commercial application of this technology could be in the development of advanced electronic devices such as smartphones, tablets, and other portable electronics where space optimization and efficient communication are essential.
Possible Prior Art
One possible prior art for this technology could be the development of multi-chip modules (MCMs) which also involve the integration of multiple semiconductor chips within a single package.
Unanswered Questions
How does this technology compare to existing semiconductor packaging solutions on the market?
This technology offers a more compact and efficient way of integrating multiple semiconductor chips within a single package, potentially leading to improved performance and reduced size of electronic devices.
What are the potential challenges in implementing this technology in mass production?
Some potential challenges in mass production could include ensuring the reliability and durability of the connections between different components within the package, as well as optimizing the manufacturing process to reduce costs and increase efficiency.
Original Abstract Submitted
Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.
