18422220. DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
- 1 DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Wei-Jhih Mao of Taipei City (TW)
Kuei-Sung Chang of Kaohsiung City (TW)
Shang-Ying Tsai of Pingzhen City (TW)
DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18422220 titled 'DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS
Simplified Explanation
The present disclosure describes an integrated chip with die stopper bumps and adhesive structures for improved stability and reliability.
- The integrated chip includes a substrate and a first die placed on top of the substrate.
- A first plurality of die stopper bumps are positioned along the backside of the first die, directly contacting it.
- The die stopper bumps are arranged in groups for enhanced support and protection.
- Adhesive structures surround each group of die stopper bumps, further securing the first die in place.
Potential Applications
The technology described in this patent application could be used in various electronic devices such as smartphones, tablets, and computers to improve the durability and longevity of integrated chips.
Problems Solved
This innovation addresses the issue of potential damage or displacement of the first die in an integrated chip due to external factors or stress, ensuring the overall reliability and performance of the device.
Benefits
The integration of die stopper bumps and adhesive structures enhances the structural integrity of the integrated chip, leading to increased stability and longevity of electronic devices.
Potential Commercial Applications
This technology could be valuable for semiconductor manufacturers looking to enhance the quality and reliability of their products, potentially leading to increased market share and customer satisfaction.
Possible Prior Art
One possible prior art could be the use of die attach materials or techniques to secure dies in integrated chips, but the specific combination of die stopper bumps and adhesive structures as described in this patent application may be a novel approach.
Unanswered Questions
How does the arrangement of die stopper bumps in groups contribute to the overall stability of the integrated chip?
The specific grouping of die stopper bumps may provide additional support and reinforcement to the first die, but the exact mechanism and impact on chip performance are not detailed in the abstract.
What materials are typically used for the die stopper bumps and adhesive structures in integrated chips?
The abstract does not specify the materials used for the die stopper bumps and adhesive structures, leaving room for further exploration into the composition and properties of these components.
Original Abstract Submitted
In some embodiments, the present disclosure relates to an integrated chip including a substrate and a first die disposed over the substrate. A first plurality of die stopper bumps are disposed along a backside of the first die. The first plurality of die stopper bumps directly contact the backside of the first die, and the first plurality of die stopper bumps are arranged as a plurality of groups of die stopper bumps. A plurality of adhesive structures are also present. Each of the plurality of adhesive structures surrounds a corresponding group of the plurality of groups of die stopper bumps.
