18421681. GATE RESISTANCE REDUCTION THROUGH LOW-RESISTIVITY CONDUCTIVE LAYER simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

GATE RESISTANCE REDUCTION THROUGH LOW-RESISTIVITY CONDUCTIVE LAYER

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Chung-Chiang Wu of Taichung City (TW)

Po-Cheng Chen of Jiaoxi Township (TW)

Kuo-Chan Huang of Hsinchu (TW)

Hung-Chin Chung of Pingzhen City (TW)

Hsien-Ming Lee of Changhua (TW)

Chien-Hao Chen of Chuangwei Township (TW)

GATE RESISTANCE REDUCTION THROUGH LOW-RESISTIVITY CONDUCTIVE LAYER - A simplified explanation of the abstract

This abstract first appeared for US patent application 18421681 titled 'GATE RESISTANCE REDUCTION THROUGH LOW-RESISTIVITY CONDUCTIVE LAYER

Simplified Explanation

The patent application describes a device with a semiconductor fin and a gate stack on the sidewalls and top surface of the fin. The gate stack includes a high-k dielectric layer, a work-function layer, a blocking layer, and a low-resistance metal layer. A gate spacer contacts the sidewall of the gate stack.

• The device includes a semiconductor fin and a gate stack with multiple layers on the fin.
• The gate stack consists of a high-k dielectric layer, a work-function layer, a blocking layer, and a low-resistance metal layer.
• The low-resistance metal layer has a lower resistivity value than the work-function layer and the blocking layer.
• A gate spacer is in contact with the sidewall of the gate stack.

Potential Applications

This technology could be applied in the development of advanced semiconductor devices, such as high-performance transistors for use in integrated circuits.

Problems Solved

This technology helps in improving the performance and efficiency of semiconductor devices by reducing resistance and enhancing control over the flow of current.

Benefits

The use of a low-resistance metal layer in the gate stack can lead to faster operation, lower power consumption, and overall improved functionality of the semiconductor device.

Potential Commercial Applications

The technology could find applications in the manufacturing of various electronic devices, including smartphones, computers, and other consumer electronics, to enhance their performance and energy efficiency.

Possible Prior Art

Prior art may include patents or publications related to gate stack structures in semiconductor devices, particularly those focusing on reducing resistance and improving performance.

How does this technology compare to existing gate stack structures in terms of performance and efficiency?

This article does not provide a direct comparison with existing gate stack structures to evaluate the performance and efficiency improvements offered by the described technology.

What specific semiconductor devices or applications could benefit the most from this innovation?

The article does not specify the targeted semiconductor devices or applications that could derive the greatest benefits from implementing this technology.

Original Abstract Submitted

A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.