18421198. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Jayeon Lee of Seongnam-si (KR)
Jae-eun Lee of Hwaseong-si (KR)
Yeongkwon Ko of Hwaseong-si (KR)
Teak Hoon Lee of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18421198 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The semiconductor package described in the patent application includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate has a cavity and a vent hole that extends from the top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the vent hole to fill the cavity.
- Package substrate with cavity and vent hole
- First semiconductor chip mounted on the package substrate
- Second semiconductor chip mounted on top of the first semiconductor chip
- First under-fill layer filling the space between the package substrate and the first semiconductor chip
Potential Applications
The technology described in this patent application could be applied in the semiconductor industry for the fabrication of advanced semiconductor packages with improved thermal management and reliability.
Problems Solved
This technology solves the problem of thermal management in semiconductor packages by providing a structure that allows for efficient heat dissipation and improved reliability of the overall package.
Benefits
The benefits of this technology include enhanced thermal performance, increased reliability, and potentially longer lifespan of semiconductor packages.
Potential Commercial Applications
One potential commercial application of this technology could be in the production of high-performance computing devices, such as servers and data centers, where efficient thermal management is crucial for optimal performance.
Possible Prior Art
One possible prior art for this technology could be the use of under-fill layers in semiconductor packaging to improve thermal performance and reliability. However, the specific structure involving a cavity and vent hole in the package substrate may be a novel aspect of this innovation.
Unanswered Questions
How does the presence of the cavity and vent hole affect the overall performance of the semiconductor package?
The presence of the cavity and vent hole in the package substrate is designed to improve thermal management, but the specific impact on performance metrics such as heat dissipation efficiency and reliability is not explicitly discussed in the abstract.
Are there any limitations or drawbacks associated with the proposed semiconductor package design?
While the abstract highlights the benefits of the technology, it does not mention any potential limitations or drawbacks that may arise from implementing this specific semiconductor package design.
Original Abstract Submitted
Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.
