18420404. Programmable Memory Timing simplified abstract (Micron Technology, Inc.)
Contents
- 1 Programmable Memory Timing
Programmable Memory Timing
Organization Name
Inventor(s)
Kang-Yong Kim of Boise ID (US)
Timothy M. Hollis of Meridian ID (US)
Dong Soon Lim of Boise ID (US)
Programmable Memory Timing - A simplified explanation of the abstract
This abstract first appeared for US patent application 18420404 titled 'Programmable Memory Timing
Simplified Explanation
The patent application describes apparatuses and methods for establishing relative delays between different data lines in order to mitigate simultaneous switching output (SSO) and crosstalk issues that can impact channel timing budget parameters. The system includes an interconnect with multiple data lines connecting a host device to a memory device. The host device can transmit a command indicating a phase offset between data lines, and the memory device can adjust the relative phase offsets between data lines accordingly. The system can activate these phase offsets based on frequency.
- Communication between host device and memory device to establish relative delays between data lines
- Mitigate simultaneous switching output (SSO) and crosstalk issues
- Interconnect with multiple data lines connecting host device to memory device
- Host device transmits command indicating phase offset between data lines
- Memory device adjusts relative phase offsets between data lines
- Activation of phase offsets based on frequency
Potential Applications
This technology can be applied in high-speed data transmission systems, memory controllers, and other devices where precise timing between data lines is critical.
Problems Solved
This technology addresses issues related to simultaneous switching output (SSO) and crosstalk that can impact channel timing budget parameters in data transmission systems.
Benefits
The benefits of this technology include improved data transmission reliability, reduced signal interference, and optimized channel timing budget parameters.
Potential Commercial Applications
Potential commercial applications of this technology include high-speed data communication systems, memory devices, and other electronic devices requiring precise timing control for data transmission.
Possible Prior Art
One possible prior art could be methods for adjusting phase offsets in data transmission systems to optimize signal integrity and timing parameters.
Unanswered Questions
How does this technology compare to existing methods for mitigating SSO and crosstalk issues in data transmission systems?
This technology offers a unique approach by enabling communication between the host device and memory device to establish relative delays between data lines. This allows for precise adjustment of phase offsets to address SSO and crosstalk issues.
What impact does the activation of phase offsets based on frequency have on overall system performance and efficiency?
By activating phase offsets based on frequency, the system can dynamically adjust timing parameters to optimize data transmission under varying conditions. This can potentially improve system performance and efficiency in high-speed data communication applications.
Original Abstract Submitted
Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.
