18420074. CHOPLESS FLOW FOR STAIRLESS ELECTRICAL INTERCONNECT STRUCTURE simplified abstract (Micron Technology, Inc.)
Contents
CHOPLESS FLOW FOR STAIRLESS ELECTRICAL INTERCONNECT STRUCTURE
Organization Name
Inventor(s)
Surendranath C. Eruvuru of Boise ID (US)
CHOPLESS FLOW FOR STAIRLESS ELECTRICAL INTERCONNECT STRUCTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18420074 titled 'CHOPLESS FLOW FOR STAIRLESS ELECTRICAL INTERCONNECT STRUCTURE
The abstract describes a patent application for a stairless electrical interconnect structure with contact pillars embedded within a periodic material stack to provide electrical connections to access lines associated with a three-dimensional memory array.
- Contact pillars are formed in a corresponding array of vertical contact pillar trenches etched into the material stack in two stages.
- Depths of the trenches vary between columns by a fixed number of tiers and then offset the depths between rows.
Potential Applications: - Three-dimensional memory arrays - Integrated circuit design - Semiconductor manufacturing
Problems Solved: - Providing electrical connections in a three-dimensional memory array - Efficiently accessing multiple tiers in a material stack
Benefits: - Improved electrical interconnectivity - Space-saving design - Enhanced performance in memory arrays
Commercial Applications: Title: Innovative Electrical Interconnect Structure for Three-Dimensional Memory Arrays This technology can be applied in the semiconductor industry for the development of advanced memory arrays, leading to faster and more efficient electronic devices.
Prior Art: Researchers can explore prior patents related to electrical interconnect structures in memory arrays to understand the existing technology landscape.
Frequently Updated Research: Researchers in the field of semiconductor manufacturing may be conducting studies on optimizing electrical interconnect structures for memory arrays. Stay updated on the latest advancements in this area.
Questions about Electrical Interconnect Structures for Memory Arrays: 1. How does the depth variation of contact pillar trenches impact the performance of the electrical interconnect structure? 2. What are the key differences between traditional stair-based interconnect structures and the stairless design described in the patent application?
Original Abstract Submitted
A stairless electrical interconnect structure with contact pillars embedded within and collectively accessing each tier in a periodic material stack, e.g., to provide electrical connections to access lines associated with a three-dimensional memory array, is described. The contact pillars can be formed in a corresponding array of vertical contact pillar trenches etched into the material stack in two stages to create depths of the trenches that vary between columns by a fixed number of tiers and then offset the depths between rows.
