18417709. NAND STAIRCASE LANDING PADS CONVERSION simplified abstract (Micron Technology, Inc.)

NAND STAIRCASE LANDING PADS CONVERSION

Organization Name

Micron Technology, Inc.

Inventor(s)

Mojtaba Asadirad of Boise ID (US)

Yiping Wang of Boise ID (US)

David H. Wells of Boise ID (US)

Matt J. King of Boise ID (US)

NAND STAIRCASE LANDING PADS CONVERSION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18417709 titled 'NAND STAIRCASE LANDING PADS CONVERSION

Simplified Explanation

The patent application describes methods, systems, and devices for converting NAND staircase landing pads in memory devices. It introduces lateral word line contacts that connect a word line with a conductive pillar, reducing the need for direct placement of the pillar on the word line. This architecture also allows the target word line to be connected to CMOS circuitry through a single conductive pillar, minimizing errors and reducing the total number of pillars.

• Memory device architecture with lateral word line contacts
• Conductive pillars connecting word lines without direct placement
• Reduction in the total quantity of conductive pillars
• Connection of target word line to CMOS circuitry with a single pillar
• Lower risk of manufacturing errors

Key Features and Innovation

• Introduction of lateral word line contacts in memory devices
• Use of conductive pillars to connect word lines without direct placement
• Reduction in the total number of conductive pillars required
• Simplified connection of target word line to CMOS circuitry with a single pillar
• Lower risk of manufacturing errors in memory device production

Potential Applications

This technology can be applied in various memory devices, particularly in NAND flash memory architectures. It can enhance the efficiency and reliability of memory devices by simplifying the connection between word lines and conductive pillars.

Problems Solved

• Simplifies the connection between word lines and conductive pillars in memory devices
• Reduces the risk of errors in manufacturing processes
• Minimizes the total quantity of conductive pillars required in memory device architecture

Benefits

• Improved efficiency and reliability of memory devices
• Simplified architecture for connecting word lines and conductive pillars
• Reduced risk of errors in manufacturing processes
• Cost-effective solution for memory device production

Commercial Applications

Memory device manufacturers can benefit from this technology by implementing more efficient and reliable memory architectures. This innovation can lead to cost savings in production processes and improved performance in memory devices.

Questions about NAND Staircase Landing Pads Conversion

How does the use of lateral word line contacts improve the connection between word lines and conductive pillars in memory devices?

The lateral word line contacts allow for a more efficient and reliable connection between word lines and conductive pillars by eliminating the need for direct placement of the pillars on the word lines.

What are the potential implications of reducing the total quantity of conductive pillars in memory device architecture?

By reducing the total number of conductive pillars required, memory device manufacturers can lower production costs and minimize the risk of errors in manufacturing processes.

Original Abstract Submitted

Methods, systems, and devices for NAND staircase landing pads conversion are described. A memory device may include one or more lateral word line contacts that may couple a word line with a conductive pillar that traverses a stack of materials of the memory device. The use of the lateral word line contact may allow for a conductive pillar to be coupled with a target word line without requiring an end of the conductive pillar to be placed directly on the word line. Additionally, the memory architecture described herein may allow for the target word line to be coupled with CMOS circuitry via a first conductive pillar without the use of a second conductive pillar, as the first conductive pillar may traverse the stack of materials and be coupled with the CMOS circuitry. Therefore, total quantity of conductive pillars may be reduced, and the risk of manufacturing errors may be lowered.