18416508. TRENCH CONTACT STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION simplified abstract (Intel Corporation)

TRENCH CONTACT STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Organization Name

Intel Corporation

Inventor(s)

Subhash M. Joshi of Hillsboro OR (US)

Jeffrey S. Leib of Beaverton OR (US)

Michael L. Hattendorf of Portland OR (US)

TRENCH CONTACT STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18416508 titled 'TRENCH CONTACT STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Simplified Explanation

The patent application describes an integrated circuit structure fabrication method for 10 nanometer node and smaller structures, involving a fin, gate dielectric layer, gate electrode, semiconductor source/drain regions, and trench contact structures.

• The integrated circuit structure includes a fin, gate dielectric layer, gate electrode, semiconductor source/drain regions, and trench contact structures.
• The gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin.
• The gate electrode is over the gate dielectric layer, the top of the fin, and laterally adjacent the sidewalls of the fin.
• First and second semiconductor source/drain regions are adjacent the first and second sides of the gate electrode, respectively.
• First and second trench contact structures are over the first and second semiconductor source/drain regions, respectively, comprising a U-shaped metal layer and a T-shaped metal layer.

Potential Applications

This technology can be applied in the manufacturing of advanced integrated circuits for various electronic devices, such as smartphones, tablets, computers, and other consumer electronics.

Problems Solved

This technology solves the problem of fabricating smaller and more efficient integrated circuit structures for high-performance electronic devices, enabling faster processing speeds and improved power efficiency.

Benefits

The benefits of this technology include increased performance, reduced power consumption, and enhanced functionality of electronic devices that use these advanced integrated circuit structures.

Potential Commercial Applications

The potential commercial applications of this technology include the semiconductor industry, electronics manufacturers, and companies producing high-performance computing devices.

Possible Prior Art

One possible prior art for this technology could be the fabrication methods used for previous generations of integrated circuit structures, such as those for 14nm or 7nm nodes.

How does this technology compare to existing fabrication methods for integrated circuit structures?

This article does not provide a direct comparison to existing fabrication methods for integrated circuit structures, leaving the reader to wonder about the specific advantages and differences between this technology and current practices.

What are the specific performance improvements that can be expected from implementing this technology in electronic devices?

The article does not detail the specific performance improvements that can be expected from implementing this technology in electronic devices, leaving the reader curious about the potential speed, power efficiency, and other enhancements that could result.

Original Abstract Submitted

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.