18413115. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Moonyong Jang of Suwon-si (KR)
Keunyoung Lee of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18413115 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the abstract includes a first substrate with multiple wire layers stacked vertically, chip stack structures arranged in a first direction, a processor chip, and chip-to-chip wires connecting the closest chip stack structure to the processor chip.
- The semiconductor package features wire layers stacked vertically and chip stack structures arranged in a specific direction.
- The processor chip is placed on the first substrate, enhancing connectivity within the package.
- Chip-to-chip wires connect the closest chip stack structure to the processor chip, optimizing data transfer.
- Each chip stack structure contains semiconductor chips offset-stacked in the first direction, improving efficiency.
- The wires within the chip stack structures connect the semiconductor chips, ensuring seamless communication.
Potential Applications: This technology can be applied in high-performance computing systems, data centers, and advanced electronic devices requiring efficient data transfer and connectivity.
Problems Solved: This innovation addresses the need for improved connectivity and data transfer speeds in semiconductor packages, enhancing overall performance and efficiency.
Benefits: The technology offers enhanced connectivity, improved data transfer speeds, and optimized performance in electronic devices and computing systems.
Commercial Applications: This technology can be utilized in the development of high-speed processors, advanced electronic devices, and data centers, catering to industries requiring efficient data processing and connectivity solutions.
Questions about the technology: 1. How does the offset-stacked semiconductor chip design improve performance in the semiconductor package? 2. What are the potential challenges in implementing this technology in commercial electronic devices?
Original Abstract Submitted
Embodiments of the present disclosure include a semiconductor package comprising a first substrate including a plurality of wires stacked in a plurality of layers in a vertical direction, a plurality of chip stack structures spaced apart from each other on the first substrate and arranged in a first direction, a processor chip disposed on the first substrate, and a chip-to-chip wire connecting a chip stack structure that is disposed closest to the processor chip among the plurality of chip stack structures, wherein each of the plurality of chip stack structures includes a plurality of semiconductor chips offset-stacked in the first direction and a plurality of wires connecting the plurality of semiconductor chips to one another.
