18410728. COMPUTER AND METHOD simplified abstract (Toshiba Tec Kabushiki Kaisha)
Contents
COMPUTER AND METHOD
Organization Name
Inventor(s)
Naoya Sato of Izunokuni Shizuoka (JP)
COMPUTER AND METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 18410728 titled 'COMPUTER AND METHOD
Simplified Explanation: The patent application describes a computer system that can execute bytecode with or without optimization for an extended Instruction Set Architecture (ISA) supported by the CPU, based on a designated command line argument.
Key Features and Innovation:
- Storage device stores operating system that executes bytecode without optimization for extended ISA unless designated in a command line argument.
- Correspondence table shows relationship between extension field value indicating extended ISA and command line argument enabling optimization.
- Program in storage device causes CPU to automatically include command line argument for extended ISA when executing bytecode.
Potential Applications: This technology can be used in various computing systems where optimization for specific ISAs is required, such as in high-performance computing, embedded systems, and virtual machines.
Problems Solved: This technology addresses the need for efficient execution of bytecode on CPUs supporting extended ISAs, allowing for better performance and resource utilization.
Benefits:
- Improved performance by optimizing bytecode execution for specific ISAs.
- Flexibility to enable or disable optimization based on designated command line arguments.
- Enhanced compatibility with a wide range of CPUs supporting different ISAs.
Commercial Applications: Potential commercial applications include software development tools, virtualization platforms, and cloud computing services that require efficient execution of bytecode on diverse CPU architectures.
Prior Art: Researchers can explore prior patents related to optimizing bytecode execution on CPUs with support for extended ISAs to understand the existing technology landscape.
Frequently Updated Research: Stay updated on advancements in optimizing bytecode execution for various ISAs, as well as developments in CPU architectures supporting extended ISAs.
Questions about Bytecode Optimization: 1. How does the automatic inclusion of command line arguments improve bytecode execution on CPUs with extended ISAs? 2. What are the implications of enabling optimization for specific ISAs in terms of overall system performance and resource utilization?
Original Abstract Submitted
According to one embodiment, a computer includes a CPU and a storage device. The storage device stores an operating system that executes a bytecode without optimization for an extended ISA supported by the CPU unless the extended ISA is designated in a command line argument for executing the bytecode. The storage device further stores a correspondence table showing a correspondence between a value of an extension field indicating the extended ISA and the command line argument enabling optimization corresponding to the extended ISA. A program in the storage device is configured to cause the CPU to acquire an ISA supported by the CPU, acquire the extended ISA from the ISA, refer to the correspondence table to acquire the command line argument associated with the extended ISA, and then automatically include the command line argument associated with the extended ISA when executing the bytecode.
