18405372. IMAGE SENSOR simplified abstract (Samsung Electronics Co., Ltd.)
Contents
IMAGE SENSOR
Organization Name
Inventor(s)
IMAGE SENSOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 18405372 titled 'IMAGE SENSOR
The abstract describes an image sensor with multiple semiconductor chips bonded together, each with different wiring structures and bonding pads.
- The image sensor consists of multiple semiconductor chips interconnected through bonding pads and wiring structures.
- The first semiconductor chip has a pixel unit and a wiring structure with a bonding pad.
- The second semiconductor chip has wiring structures on both surfaces, connected through a via structure, and bonded to the first chip.
- The third semiconductor chip is connected to the second chip through a bonding layer with a bonding pad.
Potential Applications: - This technology can be used in digital cameras, smartphones, and other imaging devices. - It can also be applied in medical imaging equipment and industrial inspection systems.
Problems Solved: - Improved image quality and resolution in digital imaging devices. - Enhanced connectivity and data transfer between semiconductor chips.
Benefits: - Higher performance and efficiency in image sensors. - Compact design and improved functionality in electronic devices.
Commercial Applications: - This technology can be utilized by semiconductor manufacturers, electronics companies, and camera manufacturers to enhance their products and stay competitive in the market.
Questions about the technology: 1. How does the bonding process between the semiconductor chips affect the overall performance of the image sensor? 2. What are the specific advantages of using multiple semiconductor chips in an image sensor compared to a single-chip design?
Original Abstract Submitted
An image sensor is provided. The image sensor includes a first semiconductor chip including a first semiconductor substrate having a pixel unit, a first wiring structure having a first wiring layer, and a first bonding pad; a second semiconductor chip including a second semiconductor substrate having first and second surfaces, a second wiring structure on the first surface, contacting the first wiring structure, and having a second wiring layer, a second upper bonding pad bonded to the first bonding pad, and a via structure connected to the second wiring layer and extending to the second surface; a bonding layer including a bonding insulating layer on the second surface, and a second lower bonding pad connected to the via structure; and a third semiconductor chip including a third semiconductor substrate, a third wiring structure contacting the bonding insulating layer, and a third bonding pad bonded to the second lower bonding pad.
