18400497. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Dae-Woo Kim of Seongnam-si (KR)
Eunseok Song of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18400497 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the abstract consists of two semiconductor chips with different widths, each with a wiring layer and through vias for power connection.
- The first semiconductor chip has a first wiring structure and through via for power, while the second semiconductor chip has a second wiring structure and through via for power.
- The first chip receives power through its wiring structure and through via, and the second chip receives power through its own wiring structure and through via.
Potential Applications: - This technology can be used in various electronic devices requiring power distribution between different semiconductor chips. - It can be applied in the development of advanced integrated circuits and microprocessors.
Problems Solved: - Efficient power distribution between semiconductor chips with different widths. - Enhanced performance and reliability of electronic devices.
Benefits: - Improved power management in semiconductor packages. - Increased efficiency and functionality of electronic devices.
Commercial Applications: Title: Advanced Power Distribution Technology for Semiconductor Packages This technology can be utilized in the production of high-performance computers, smartphones, and other electronic devices requiring efficient power distribution among semiconductor chips.
Questions about the technology: 1. How does the different widths of the semiconductor chips impact power distribution?
- The different widths require customized wiring structures and through vias for efficient power distribution.
2. What are the potential challenges in implementing this technology in mass production?
- Ensuring precise alignment and connection of the wiring structures and through vias in semiconductor packages may pose challenges.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.
