18400497. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 SEMICONDUCTOR PACKAGE
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Dae-Woo Kim of Seongnam-si (KR)
Eunseok Song of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18400497 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes two semiconductor chips with different widths, each with a wiring layer and through vias for power connection. The first chip receives power through its wiring structure and through via, while the second chip receives power through its own wiring structure and through via.
- The semiconductor package consists of two semiconductor chips with different widths.
- Each chip has a wiring layer and through vias for power connection.
- The first chip receives power through its wiring structure and through via.
- The second chip receives power through its wiring structure and through via.
Potential Applications
This technology could be applied in various electronic devices such as smartphones, tablets, laptops, and other portable devices where space-saving and efficient power distribution are crucial.
Problems Solved
This technology solves the problem of efficiently providing power to semiconductor chips with different widths in a compact package, ensuring optimal performance and power distribution.
Benefits
The benefits of this technology include improved power distribution efficiency, space-saving design, and enhanced performance of electronic devices.
Potential Commercial Applications
The potential commercial applications of this technology include consumer electronics, automotive electronics, industrial automation, and any other devices requiring efficient power distribution to semiconductor chips.
Possible Prior Art
One possible prior art could be semiconductor packages with through vias for power connection, but the specific implementation of providing power to chips with different widths may be a novel aspect of this technology.
Unanswered Questions
How does this technology impact overall power consumption in electronic devices?
This article does not provide information on the potential impact of this technology on the overall power consumption of electronic devices. Further research and testing may be needed to determine the efficiency gains in power consumption.
What are the potential challenges in integrating this technology into existing semiconductor packaging processes?
The article does not address the potential challenges in integrating this technology into existing semiconductor packaging processes. Factors such as compatibility, cost, and manufacturing complexity could be significant challenges that need to be explored further.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.
