18400082. MEMORY DEVICE HAVING 2-TRANSISTOR MEMORY CELL AND ACCESS LINE PLATE simplified abstract (Micron Technology, Inc.)

From WikiPatents
Jump to navigation Jump to search

MEMORY DEVICE HAVING 2-TRANSISTOR MEMORY CELL AND ACCESS LINE PLATE

Organization Name

Micron Technology, Inc.

Inventor(s)

Kamal M. Karda of Boise ID (US)

Karthik Sarpatwari of Boise ID (US)

Haitao Liu of Boise ID (US)

Durai Vishak Nirmal Ramaswamy of Boise ID (US)

MEMORY DEVICE HAVING 2-TRANSISTOR MEMORY CELL AND ACCESS LINE PLATE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18400082 titled 'MEMORY DEVICE HAVING 2-TRANSISTOR MEMORY CELL AND ACCESS LINE PLATE

Simplified Explanation

The patent application describes an apparatus and method involving a substrate, a pillar, two conductive plates, a memory cell, and a conductive connection. The memory cell is positioned between the conductive plates and is electrically separated from them.

  • The apparatus includes a pillar perpendicular to the substrate, with two conductive plates on different levels separated by dielectrics.
  • The memory cell consists of semiconductor materials contacting the pillar and the conductive connection.
  • The innovation involves the unique arrangement of components within the apparatus.

Key Features and Innovation

  • Apparatus with a pillar, conductive plates, memory cell, and conductive connection.
  • Memory cell electrically separated from the conductive plates.
  • Semiconductor materials in the memory cell contacting the pillar and conductive connection.

Potential Applications

The technology could be used in:

  • Memory storage devices
  • Semiconductor manufacturing
  • Integrated circuits

Problems Solved

  • Efficient memory cell design
  • Improved electrical separation
  • Enhanced semiconductor material contact

Benefits

  • Increased memory storage capacity
  • Enhanced semiconductor performance
  • Improved device reliability

Commercial Applications

  • Title: "Innovative Memory Cell Technology for Semiconductor Devices"
  • Potential commercial uses in electronics, data storage, and computing industries.
  • Market implications include improved memory devices and semiconductor products.

Prior Art

No prior art information available at this time.

Frequently Updated Research

No frequently updated research relevant to this technology at present.

Questions about Memory Cell Technology

Question 1

How does the memory cell technology improve semiconductor performance?

The memory cell technology enhances semiconductor performance by optimizing the contact between semiconductor materials and the conductive connection, leading to improved device reliability and efficiency.

Question 2

What are the potential applications of this innovative memory cell technology in the semiconductor industry?

The innovative memory cell technology could find applications in memory storage devices, semiconductor manufacturing processes, and integrated circuits, offering enhanced performance and efficiency in various semiconductor products.


Original Abstract Submitted

Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.