18397891. MULTI-CHIP PACKAGING simplified abstract (Intel Corporation)
Contents
- 1 MULTI-CHIP PACKAGING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MULTI-CHIP PACKAGING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
MULTI-CHIP PACKAGING
Organization Name
Inventor(s)
Robert L. Sankman of Phoenix AZ (US)
Sairam Agraharam of Chandler AZ (US)
Shengquan Ou of Chandler AZ (US)
Thomas J. De Bonis of Tempe AZ (US)
Todd Spencer of Chandler AZ (US)
Guotao Wang of Chandler AZ (US)
MULTI-CHIP PACKAGING - A simplified explanation of the abstract
This abstract first appeared for US patent application 18397891 titled 'MULTI-CHIP PACKAGING
Simplified Explanation
The abstract describes an electronic device with two dies connected by a bridge interconnect, facilitating electrical communication between them.
- The electronic device includes a first die with a set of die contacts.
- The device also includes a second die with a second set of die contacts.
- A bridge interconnect is present with a first set of bridge contacts directly coupled to the first set of die contacts and a second set of bridge contacts directly coupled to the second set of die contacts.
- The bridge interconnect helps in enabling electrical communication between the first die and the second die.
Potential Applications
This technology could be applied in:
- Integrated circuits
- Microprocessors
- Memory modules
Problems Solved
- Facilitates electrical communication between different components in an electronic device.
- Helps in improving the overall performance and functionality of the device.
Benefits
- Enhanced connectivity between dies.
- Increased efficiency in data transfer.
- Compact design for electronic devices.
Potential Commercial Applications
Optimizing Electronic Device Connectivity for Improved Performance
Possible Prior Art
No known prior art.
Unanswered Questions
How does the bridge interconnect impact the overall power consumption of the electronic device?
The abstract does not provide information on the power efficiency of the bridge interconnect.
Are there any limitations to the size or scale of the electronic device that can utilize this technology?
The abstract does not mention any restrictions on the size or scale of devices that can implement this technology.
Original Abstract Submitted
An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
