18395192. TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF FABRICATION simplified abstract (Intel Corporation)

TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF FABRICATION

Organization Name

Intel Corporation

Inventor(s)

Gilbert Dewey of Hillsboro OR (US)

Ryan Keech of Portland OR (US)

Cory Bomberger of Portland OR (US)

Cheng-Ying Huang of Hillsboro OR (US)

Ashish Agrawal of Hillsboro OR (US)

Willy Rachmady of Beaverton OR (US)

Anand Murthy of Portland OR (US)

TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF FABRICATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18395192 titled 'TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF FABRICATION

Simplified Explanation

The patent application describes a device with a transistor made of group III-V or group IV semiconductor material, with separate source and drain structures and a gate structure in between. The device level includes a metallization structure connected to the semiconductor device.

• The device includes a transistor with a body made of single crystal group III-V or group IV semiconductor material.
• The transistor has a source structure on one portion of the body and a drain structure on another portion, with a gate structure in between.
• The gate structure consists of a first gate structure portion in a recess in the body and a second gate structure portion between the source and drain structures.
• A source contact is connected to the source structure, and a drain contact is connected to the drain structure, with the source contact in contact with the metallization structure in the device level.

Potential Applications

This technology could be applied in:

• High-performance electronic devices
• Advanced semiconductor manufacturing processes

Problems Solved

This technology helps in:

• Improving transistor performance
• Enhancing device integration and miniaturization

Benefits

The benefits of this technology include:

• Increased efficiency and speed of electronic devices
• Better control and reliability of semiconductor components

Potential Commercial Applications

The potential commercial applications of this technology could be in:

• Consumer electronics
• Telecommunications industry

Possible Prior Art

One possible prior art for this technology could be the use of similar semiconductor materials in transistor manufacturing processes.

How does this technology compare to traditional transistor designs?

This article does not provide a direct comparison between this technology and traditional transistor designs.

What are the specific performance improvements seen with this innovation?

The article does not detail the specific performance improvements achieved with this innovation.

Original Abstract Submitted

A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.