18390258. VERTICAL TYPE MEMORY DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
VERTICAL TYPE MEMORY DEVICE
Organization Name
Inventor(s)
Hyunmook Choi of Suwon-si (KR)
VERTICAL TYPE MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18390258 titled 'VERTICAL TYPE MEMORY DEVICE
The abstract describes a vertical type memory device with two pillar structures: one in a channel hole inside a word line mold, and the other in a string select line hole overlapping the channel hole inside a string select line mold.
- The first pillar structure includes a first gate insulating layer, a cell channel layer, a variable resistance layer, a first filling insulating layer, and a connection pad.
- The second pillar structure includes a second gate insulating layer, a select channel layer, and a second filling insulating layer.
Potential Applications: - Memory storage devices - Semiconductor industry - Data storage solutions
Problems Solved: - Enhanced memory storage capacity - Improved data retention and retrieval speed
Benefits: - Increased efficiency in data storage - Higher performance in memory devices - Potential for smaller, more compact memory solutions
Commercial Applications: - Memory chip manufacturing - Data centers - Consumer electronics industry
Questions about Vertical Type Memory Device: 1. How does the vertical type memory device improve data storage efficiency? 2. What are the key components of the pillar structures in this memory device?
Frequently Updated Research: - Ongoing advancements in memory device technology - Research on improving data storage capabilities in semiconductor devices
Original Abstract Submitted
A vertical type memory device includes a first pillar structure in a channel hole inside a word line mold, and a second pillar structure in a string select line hole overlapping the channel hole inside a string select line mold. The first pillar structure includes a first gate insulating layer and a cell channel layer on an inner wall of the channel hole, a variable resistance layer on one side of the cell channel layer, a first filling insulating layer filling the channel hole, and a connection pad in an upper portion of the first filling insulating layer. The second pillar structure includes a second gate insulating layer on an inner wall of the string select line hole, a select channel layer on one side of the second gate insulating layer, and a second filling insulating layer filling the string select line hole on the select channel layer.
