18388506. READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME simplified abstract (Micron Technology, Inc.)
Contents
- 1 READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME
Organization Name
Inventor(s)
Yu-Chung Lien of San Jose CA (US)
Zhenming Zhou of San Jose CA (US)
READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18388506 titled 'READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME
Simplified Explanation
The method described in the abstract involves compensating for partial block read in a memory device by adjusting voltages applied to the wordline and bitline connected to a specified memory cell in a string of series-connected memory cells.
- Receiving a read request specifying a memory cell in an array of memory cells on a memory device.
- Ramping the voltage applied to the wordline connected to the specified memory cell to a predetermined value.
- Ramping the voltage applied to the bitline connected to the specified memory cell to a predetermined value.
- Comparing the current along the string of memory cells with a reference current using a current comparator to generate an analog output signal.
- Applying a voltage offset to the read voltage level during a sensing operation based on the analog output signal.
Potential Applications
This technology can be applied in various memory devices such as flash memory, solid-state drives, and other non-volatile memory systems where partial block read compensation is required.
Problems Solved
This technology solves the problem of inaccuracies in reading data from memory cells due to variations in cell characteristics and environmental conditions.
Benefits
- Improved accuracy in reading data from memory cells. - Enhanced reliability of memory devices. - Increased performance in memory operations.
Potential Commercial Applications
Optimizing memory devices for better performance and reliability in applications such as data storage, consumer electronics, and automotive systems.
Possible Prior Art
One possible prior art could be techniques for read disturb mitigation in memory devices, where similar methods may have been used to compensate for partial block reads.
Unanswered Questions
How does this method impact the overall speed of memory read operations?
The abstract does not provide specific details on how the compensation method affects the speed of memory read operations. Further information on the impact on read speed would be beneficial for understanding the overall performance of the technology.
Are there any limitations or constraints in implementing this method in different types of memory devices?
The abstract does not mention any limitations or constraints that may arise when implementing this compensation method in various memory devices. Exploring potential challenges in applying the method to different memory technologies would provide a more comprehensive understanding of its practicality and versatility.
Original Abstract Submitted
A method for partial block read compensation can include receiving a read request that specifies a memory cell connected to a string of series-connected memory cells in an array of memory cells on a memory device, the string located at an intersection of a wordline and a bitline, and causing a first voltage applied to the wordline to which the specified memory cell is connected to ramp to a first predetermined value. The method can include causing a second voltage applied to the bitline to which the specified memory cell is connected to ramp to a second predetermined value, and can include comparing, using a current comparator, a current along the string with a reference current to generate an analog output signal. It can also include causing a voltage offset, based on the analog output signal, to be applied to a read voltage level during a sensing operation.
