18380800. STAGE CIRCUIT simplified abstract (Samsung Display Co., LTD.)
Contents
STAGE CIRCUIT
Organization Name
Inventor(s)
Il Hun Jeong of Yongin-si (KR)
Hye Sung Kim of Yongin-si (KR)
STAGE CIRCUIT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18380800 titled 'STAGE CIRCUIT
Simplified Explanation
The stage circuit described in the abstract is a complex electronic circuit that controls voltages at different nodes based on various input signals. Here is a simplified explanation of the abstract:
- An input unit receives a gate start pulse or a carry signal to control the voltage of a first node.
- A clock signal is input to the first output unit, which supplies a scan signal to the first output terminal corresponding to the voltages of the first and second nodes.
- A second output unit receives a carry clock signal and supplies a carry signal to the second output terminal corresponding to the voltages of the first and second nodes.
- Two control units control the voltages of two additional nodes based on power input.
Potential Applications: - Integrated circuits - Digital signal processing - Microprocessors
Problems Solved: - Efficient voltage control in complex circuits - Signal processing in electronic devices
Benefits: - Improved circuit performance - Enhanced signal processing capabilities - Increased efficiency in power management
Potential Commercial Applications: - Semiconductor industry - Electronics manufacturing - Telecommunications sector
Possible Prior Art: - Previous stage circuits with similar voltage control mechanisms - Existing integrated circuit designs with carry signal processing capabilities
Unanswered Questions: 1. How does the stage circuit handle potential signal interference or noise? 2. What are the specific technical specifications and limitations of the circuit in terms of voltage control and signal processing?
Original Abstract Submitted
A stage circuit includes an input unit connected to a first input terminal receiving a gate start pulse or a previous stage carry signal to control a voltage of a first node, a first output unit connected to a fourth input terminal to which a clock signal is input and supplying a scan signal to a first output terminal corresponding to a voltage of the first node and a second node, a second output unit connected to a third input terminal to which a second carry clock signal is input and supplying a carry signal to a second output terminal corresponding to the voltage of the first node and the second node, a first control unit connected to a first power input terminal to which first power is input and controlling a voltage of a third node, and a second control unit connected to a second power input terminal.
