18377777. LOW POWER FLIP-FLOP simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 LOW POWER FLIP-FLOP
LOW POWER FLIP-FLOP
Organization Name
Inventor(s)
Byounggon Kang of Suwon-si (KR)
LOW POWER FLIP-FLOP - A simplified explanation of the abstract
This abstract first appeared for US patent application 18377777 titled 'LOW POWER FLIP-FLOP
Simplified Explanation
The low power flip-flop described in the patent application includes a master section with a multiplexer, two AND-OR-Inverter (AOI) gate circuits, and an inverter circuit. It also has a slave section with two AOI gate circuits and an inverter circuit. The flip-flop is designed to receive various input signals and generate output signals efficiently.
- The flip-flop consists of a master section and a slave section, each with specific components for processing input signals and generating output signals.
- The master section includes a multiplexer, two AOI gate circuits, and an inverter circuit, while the slave section includes two AOI gate circuits and an inverter circuit.
- The flip-flop is configured to receive data input, scan input, scan enable, and inverted scan enable signals to produce internal and output signals.
- The clock signal is used by the AOI gate circuits in both sections to control the operation of the flip-flop.
Potential Applications
The technology described in this patent application could be used in various digital circuit designs where low power consumption is a priority. Some potential applications include:
- Mobile devices
- Internet of Things (IoT) devices
- Wearable technology
Problems Solved
This technology addresses the issue of power consumption in digital circuits by optimizing the design of the flip-flop to operate efficiently while still providing the necessary functionality.
Benefits
The benefits of this technology include:
- Reduced power consumption
- Improved performance
- Enhanced reliability
Potential Commercial Applications
With the increasing demand for energy-efficient electronic devices, this technology could be valuable in the following commercial applications:
- Semiconductor industry
- Consumer electronics
- Automotive electronics
Possible Prior Art
One possible prior art for this technology could be the use of traditional flip-flops in digital circuits, which may not be as power-efficient as the design described in the patent application.
Unanswered Questions
How does this technology compare to existing low power flip-flop designs on the market?
The article does not provide a direct comparison with other low power flip-flop designs, so it is unclear how this technology stands out in terms of efficiency and performance.
What are the specific power savings achieved by implementing this low power flip-flop in a digital circuit?
The article does not mention the exact power savings that can be achieved by using this technology, leaving the reader wondering about the potential energy efficiency improvements.
Original Abstract Submitted
A low power flip-flop includes a master section including a multiplexer, a first AND-OR-Inverter (AOI) gate circuit, a second AOI gate circuit, and a first inverter circuit and configured to receive a data input signal, a scan input signal, a scan enable signal, and an inverted scan enable signal, and output a second internal signal and a third internal signal, a slave section including a third AOI gate circuit, a fourth AOI gate circuit, and a second inverter circuit, and configured to receive the second and third internal signals to output an output signal, and a third inverter circuit configured to generate the inverted scan enable signal. The first to fourth AOI gate circuits are configured to receive a clock signal.
