18377530. SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER AND A BUMP simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER AND A BUMP

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Minjung Choi of Suwon-si (KR)

Sooho Shin of Hwaseong-si (KR)

Yeonjin Lee of Suwon-si (KR)

Junghoon Han of Hwaseong-si (KR)

SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER AND A BUMP - A simplified explanation of the abstract

This abstract first appeared for US patent application 18377530 titled 'SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER AND A BUMP

Simplified Explanation

The semiconductor device described in the patent application includes several components such as an interlayer insulating layer, middle interconnections, a pad, an upper interconnection, a protective insulating layer, and a bump. Here is a simplified explanation of the abstract:

• The device has an interlayer insulating layer on a substrate.
• Middle interconnections are placed within the interlayer insulating layer.
• A pad is located on top of the interlayer insulating layer.
• An upper interconnection is also present on the interlayer insulating layer.
• A protective insulating layer covers the edge of the pad, the upper interconnection, and the horizontal gap between them.
• The protective insulating layer has an opening on the pad.
• A bump is placed on the pad, extending over the protective insulating layer and overlapping the upper interconnection from a top-down view.
• The middle interconnections closest to the pad have a certain vertical thickness.
• The pad has a vertical thickness that is significantly larger than the middle interconnections.
• The gap between the pad and the upper interconnection has a length of at least 1 μm.
• The upper surface of the protective insulating layer is flat.

Potential applications of this technology:

• Semiconductor devices with improved interconnection and insulation capabilities.
• Enhanced protection for sensitive components within the device.
• Increased reliability and performance of semiconductor devices.

Problems solved by this technology:

• Ensures proper insulation and protection of the pad and upper interconnection.
• Reduces the risk of short circuits or damage to the device.
• Provides a more reliable and efficient interconnection structure.

Benefits of this technology:

• Improved overall performance and reliability of semiconductor devices.
• Enhanced protection against external factors and potential damage.
• Enables the design of more compact and efficient semiconductor devices.

Original Abstract Submitted

A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.