18368128. PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (NANYA TECHNOLOGY CORPORATION)
Contents
- 1 PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
Organization Name
Inventor(s)
WU-DER Yang of TAOYUAN CITY (TW)
PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18368128 titled 'PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
Simplified Explanation
The package structure described in the patent application includes a first substrate, a first electronic component, a second substrate, and a second electronic component. The first electronic component is connected to the first substrate through a patterned circuit layer, while the second electronic component is connected to the second substrate through a patterned circuit layer as well.
- First substrate with first electronic component connected through a patterned circuit layer
- Second substrate with second electronic component connected through a patterned circuit layer
Potential Applications
The technology described in this patent application could be applied in various electronic devices such as smartphones, tablets, laptops, and other consumer electronics where compact and efficient packaging of electronic components is required.
Problems Solved
This technology solves the problem of efficiently connecting electronic components to substrates in a compact package structure, allowing for more streamlined and space-saving designs in electronic devices.
Benefits
The benefits of this technology include improved connectivity between electronic components and substrates, leading to enhanced performance and reliability of electronic devices. Additionally, the compact package structure allows for more efficient use of space within electronic devices.
Potential Commercial Applications
- Compact electronic devices
- Consumer electronics
- IoT devices
Possible Prior Art
One possible prior art for this technology could be the use of traditional methods of connecting electronic components to substrates, which may not be as efficient or compact as the package structure described in the patent application.
Unanswered Questions
How does this technology compare to existing package structures in terms of cost-effectiveness?
The patent application does not provide information on the cost-effectiveness of this technology compared to existing package structures. Further research or analysis would be needed to determine the cost implications of implementing this technology in electronic devices.
What are the environmental implications of using this package structure in electronic devices?
The patent application does not address the environmental impact of using this package structure in electronic devices. It would be important to consider factors such as recyclability and sustainability when evaluating the overall environmental implications of this technology.
Original Abstract Submitted
A package structure and a method of manufacturing a package structure are provided. The package structure includes a first substrate, a first electronic component, a second substrate and a second electronic component. The first electronic component is disposed over a first through hole of the first substrate. The first electronic component is electrically connected to a first patterned circuit layer of the first substrate through an extending portion of the first patterned circuit layer extending beyond a sidewall of the first through hole. The second electronic component is disposed over a second through hole of the second substrate. The second electronic component is electrically connected to a second patterned circuit layer of the second substrate through an inner extending portion of the second patterned circuit layer extending beyond a sidewall of the second through hole.
