18363140. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Myung-Sung Kang of Suwon-si (KR)
Kyong Hwan Koh of Suwon-si (KR)
Chung Sun Lee of Suwon-si (KR)
Hyeon Jun Jin of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18363140 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The semiconductor package described in the patent application includes a first package substrate with a first semiconductor chip mounted on it, a second package substrate with a second semiconductor chip mounted on it, and a connection member that electrically connects the two substrates. A mold film covers the second semiconductor chip, fills a hole in the second package substrate, and covers the first semiconductor chip and the connection member on the first package substrate.
- First package substrate with first semiconductor chip
- Second package substrate with second semiconductor chip
- Connection member electrically connecting the two substrates
- Mold film covering the second semiconductor chip and filling a hole in the second package substrate
Potential Applications
The technology described in this patent application could be applied in various industries such as electronics, telecommunications, and automotive for the manufacturing of advanced semiconductor packages.
Problems Solved
This technology solves the problem of efficiently connecting multiple semiconductor chips within a single package while ensuring proper electrical connections and protection from external elements.
Benefits
The benefits of this technology include improved performance, increased reliability, and enhanced durability of semiconductor packages. It also allows for more compact and cost-effective designs.
Potential Commercial Applications
The potential commercial applications of this technology include the production of high-performance electronic devices, communication equipment, and automotive components. The technology could also be utilized in the development of advanced sensors and IoT devices.
Possible Prior Art
One possible prior art for this technology could be the use of stacked semiconductor chips in a single package with connecting elements. However, the specific configuration and design of the package described in this patent application may be novel and innovative.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods?
This article does not provide a direct comparison to existing semiconductor packaging methods, leaving the reader to wonder about the specific advantages and disadvantages of this new approach.
What are the potential limitations or challenges in implementing this technology on a large scale?
The article does not address any potential limitations or challenges in implementing this technology on a large scale, leaving room for speculation on the feasibility and practicality of mass production.
Original Abstract Submitted
Semiconductor packages and methods of fabricating the same are provided. The semiconductor package includes a first package substrate including a first area, a first semiconductor chip mounted on the first area, a second package substrate disposed on an upper surface of the first semiconductor chip and including a second area and a first hole penetrating through the second area, a second semiconductor chip mounted on the second area, a connection member electrically connecting the first package substrate and the second package substrate and between the first package substrate and the second package substrate, and a mold film covering the second semiconductor chip on the second package substrate, filling the first hole, and covering the first semiconductor chip and the connection member on the first package substrate.
